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| 型号： | ADAU1401AWBSTZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/52页 |
| 文件大小： | 0K |
| 描述： | IC AUDIO PROC 28/56BIT 48LQFP |
| 标准包装： | 2,000 |
| 系列： | SigmaDSP® |
| 类型： | 音频处理器 |
| 应用： | 监控器，电视 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
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ADAU1401A
Rev. A | Page 18 of 52
set to 0). Each of these can be turned off by writing a 1 to the
appropriate bits in this register. The ADC power-down mode
powers down both ADCs, and each DAC can be powered down
individually. The current savings is about 15 mA when the ADCs
are powered down and about 4 mA for each DAC that is powered
down. The voltage reference, which is supplied to both the ADCs
and DACs, should only be powered down if all ADCs and DACs
are powered down. The voltage reference is powered down by
setting both Bit 6 and Bit 7 of the auxiliary ADC and power
control register.
USING THE OSCILLATOR
The ADAU1401A can use an on-board oscillator to generate its
master clock. The oscillator is designed to work with a 256 × fS
master clock, which is 12.288 MHz for a fS of 48 kHz and
11.2896 MHz for a fS of 44.1 kHz. The crystal in the oscillator
circuit should be an AT-cut, parallel resonator operating at its
fundamental frequency. Figure 14 shows the external circuit
recommended for proper operation.
C1
100
MCLKI
OSCO
C2
ADAU1401A
08
50
6
-01
4
Figure 14. Crystal Oscillator Circuit
The 100 Ω damping resistor on OSCO gives the oscillator a
voltage swing of approximately 2.2 V. The crystal shunt capaci-
tance should be 7 pF. Its load capacitance should be about 18 pF,
although the circuit supports values of up to 25 pF. The necessary
values of the C1 and C2 load capacitors can be calculated from
the crystal load capacitance as follows:
STRAY
L
C
C2
C1
C2
C1
C
+
×
=
where CSTRAY is the stray capacitance in the circuit and is usually
assumed to be approximately 2 pF to 5 pF.
OSCO should not be used to drive the crystal signal directly to
another IC. This signal is an analog sine wave, and it is not appro-
priate to use it to drive a digital input. There are two options for
using the ADAU1401A to provide a master clock to other ICs in
the system. The first, and less recommended, method is to use a
high impedance input digital buffer on the OSCO signal. If this
approach is used, minimize the trace length to the buffer input.
The second method is to use a clock from the serial output port.
Pin 19 (MP11) can be set as an output (master) clock divided down
from the internal core clock. If this pin is set to serial output port
(OUTPUT_BCLK) mode in the multipurpose pin configuration
register (Address 2081) and the port is set to master in the serial
output control register (Address 2078), the desired output fre-
quency can also be set in the serial output control register with
the OBF[1:0] bits (see Table 49).
If the oscillator is not used in the design and a system master clock
is already available in the system, the oscillator can be powered
down to save power. By default, the oscillator is powered on. The
oscillator powers down when a 1 is written to the OPD bit of
the oscillator power-down register (Address 2086; see Table 60).
SETTING MASTER CLOCK/PLL MODE
The MCLKI input of the ADAU1401A feeds a PLL, which
generates the 50 MIPS SigmaDSP core clock. In normal operation,
the input to MCLKI must be one of the following: 64 × fS, 256 × fS,
384 × fS, or 512 × fS, where fS is the input sampling rate. The mode
is set by configuring PLL_MODE0 and PLL_MODE1 as described
in Table 13. If the ADAU1401A is set to receive double-rate signals
(by reducing the number of program steps per sample by a factor
of 2 using the core control register), the master clock frequency
must be 32 × fS, 128 × fS, 192 × fS, or 256 × fS. If the ADAU1401A
is set to receive quad-rate signals (by reducing the number of
program steps per sample by a factor of 4 using the DSP core
control register), the master clock frequency must be 16 × fS,
64 × fS, 96 × fS, or 128 × fS. On power-up, a clock signal must be
present on the MCLKI pin so that the ADAU1401A can complete
its initialization routine.
Table 13. PLL Modes
MCLKI Input
Frequency
PLL_MODE0
PLL_MODE1
64 × fS
0
256 × fS
0
1
384 × fS
1
0
512 × fS
1
The clock mode should not be changed without also resetting
the ADAU1401A. If the mode is changed during operation, a
click or pop may result in the output signals. The state of the
PLL_MODEx pins should be changed while RESET is held low.
The PLL loop filter should be connected to the PLL_LF pin. This
filter, shown in Figure 15, includes three passive components—
two capacitors and a resistor. The values of these components
do not need to be exact; the tolerance can be up to 10% for the
resistor and up to 20% for the capacitors. The 3.3 V signal shown in
Figure 15 can be connected to the AVDD supply of the chip.
ADAU1401A
3.3V
475
PLL_LF
56nF
3.3nF
08
50
6-
01
5
Figure 15. PLL Loop Filter
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADAU1401YSTZ | 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 类别:集成电路 (IC) >> 线性 - 音频处理 系列:SigmaDSP® 其它有关文件:STA321 View All Specifications 标准包装:1 系列:Sound Terminal™ 类型:音频处理器 应用:数字音频 安装类型:表面贴装 封装/外壳:64-LQFP 裸露焊盘 供应商设备封装:64-LQFP EP（10x10） 包装:Digi-Reel® 其它名称:497-11050-6 |
| ADAU1401YSTZ-RL | 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 类别:集成电路 (IC) >> 线性 - 音频处理 系列:SigmaDSP® 其它有关文件:STA321 View All Specifications 标准包装:1 系列:Sound Terminal™ 类型:音频处理器 应用:数字音频 安装类型:表面贴装 封装/外壳:64-LQFP 裸露焊盘 供应商设备封装:64-LQFP EP（10x10） 包装:Digi-Reel® 其它名称:497-11050-6 |
| ADAU1421YSTZ | 制造商:Analog Devices 功能描述: |
| ADAU1421YSTZ-REEL | 制造商:Analog Devices 功能描述: |
| ADAU1442 | 制造商:AD 制造商全称:Analog Devices 功能描述:SigmaDSP Digital Audio Processor |
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