参数资料
型号: ADAV4601BSTZ
厂商: Analog Devices Inc
文件页数: 14/60页
文件大小: 0K
描述: IC AUDIO CODEC PROCESSOR 80-LQFP
标准包装: 1
系列: SigmaDSP®
类型: 音频处理器
应用: TV
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(14x14)
包装: 托盘
ADAV4601
Rev. B | Page 21 of 60
I2S Mode
Right-Justified (RJ) Mode
In I2S mode, the data is left-justified, MSB first, with the MSB
placed in the second BCLK period following the transition of
the LRCLK. A high-to-low transition of the LRCLK signifies the
beginning of the left channel data transfer, and a low-to-high
transition on the LRCLK signifies the beginning of the right
channel data transfer (see Figure 27).
In RJ mode, the data is right-justified, LSB last, with the LSB
placed in the last BCLK period preceding the transition of LRCLK.
A high-to-low transition of the LRCLK signifies the beginning
of the right-channel data transfer, and a low-to-high transition
on the LRCLK signifies the beginning of the left-channel data
transfer (see Figure 29).
Left-Justified (LJ) Mode
In LJ mode, the data is left-justified, MSB first, with the MSB
placed in the first BCLK period following the transition of the
LRCLK. A high-to-low transition of the LRCLK signifies the
beginning of the right-channel data transfer, and a low-to-high
transition on the LRCLK signifies the beginning of the left-
channel data transfer (see Figure 28).
LRCLK
BCLK
SDO0
MSB
LEFT CHANNEL
LSB
MSB
RIGHT CHANNEL
LSB
1 /FS
07
0-
0
21
Figure 27. I2S Mode
LRCLK
BCLK
SDO0
LEFT CHANNEL
MSB
LSB
MSB
RIGHT CHANNEL
LSB
1 /FS
07
070
-022
Figure 28. Left-Justified Mode
LRCLK
BCLK
SDO0
LEFT CHANNEL
MSB
LSB
MSB
RIGHT CHANNEL
LSB
1 /FS
07
0
70
-02
3
Figure 29. Right-Justified Mode
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