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| 型号： | ADAV4601BSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 33/60页 |
| 文件大小： | 0K |
| 描述： | IC AUDIO CODEC PROCESSOR 80-LQFP |
| 标准包装： | 1 |
| 系列： | SigmaDSP® |
| 类型： | 音频处理器 |
| 应用： | TV |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 托盘 |
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ADAV4601
Rev. B | Page 39 of 60
Address 0x010C and Address 0x010D Tweeter Left Balance Control Registers (Default: 0x0080, 0x0000)
These two registers (0x010C and 0x010D) control the balance for the left tweeter output.
The balance control words are 28-bit words in twos complement and a 5.23 format. This means there are five bits to the left of the decimal
point of which the most significant bit is the sign bit.
To simplify updating the tweeter left balance control, the I2C address pointer auto-increments when writing and reading. This means that
the balance control register can be updated in a single I2C block write. Therefore, it is recommended that the tweeter left balance control
be updated using the following I2C write format:
<dev addr><010C><32-bit data transfer>
Note that the tweeter left balance control is a 32-bit parameter; therefore, both Register 0x010C and Register 0x010D must be written to.
Writing anything less than the 32 bits to these registers does not update the parameter.
Table 27.
Bit No.
Bit Name
Description
Default
Bits[15:12]
Reserved
Always write as 0 if writing to this register.
0000
Bits[11:0]
Tweeter left balance control register[27:0]
0x010C Bits[11:0] = tweeter left balance control register[27:16]
000010000000
Bits[15:0]
Tweeter left balance control register[27:0]
0x010D Bits[15:0] = tweeter left balance control register[15:0]
0000000000000000
Address 0x010E and Address 0x010F Tweeter Right Balance Control Registers (Default: 0x0080, 0x0000)
These two registers (0x010E and 0x010F) control the balance for the right tweeter output.
The balance control words are 28-bit words in twos complement and a 5.23 format. This means there are five bits to the left of the decimal
point of which the most significant bit is the sign bit.
Table 28.
Bit No.
Bit Name
Description
Default
Bits[15:12]
Reserved
Always write as 0 if writing to this register.
0000
Bits[11:0]
Tweeter right balance control register[27:0]
0x010E Bits[11:0] = tweeter right balance control register[27:16]
000010000000
Bits[15:0]
Tweeter right balance control register[27:0]
0x010F Bits[15:0] = tweeter right balance control register[15:0]
0000000000000000
Address 0x0110 and Address 0x0111 Woofer Left Balance Control Registers (Default: 0x0080, 0x0000)
These two registers control the balance for the left woofer output.
The balance control words are 28-bit words in twos complement and a 5.23 format. This means there are five bits to the left of the decimal
point of which the most significant bit is the sign bit.
Table 29.
Bit No.
Bit Name
Description
Default
Bits[15:12]
Reserved
Always write as 0 if writing to this register.
0000
Bits[11:0]
Woofer left balance control register[27:0]
0x0110 Bits[11:0] = woofer left balance control register[27:16]
000010000000
Bits[15:0]
Woofer left balance control register[27:0]
0x0111 Bits[15:0] = woofer left balance control register[15:0]
0000000000000000
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