参数资料
型号: ADE7166ASTZF16
厂商: Analog Devices Inc
文件页数: 138/152页
文件大小: 0K
描述: IC ENERGY METER 1PHASE 64LQFP
标准包装: 1
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
SPI INTERRUPT AND STATUS FLAGS
The SPI interface has several status flags that indicate the status
of the double-buffered receive and transmit registers. Figure 111
shows when the status and interrupt flags are raised. The transmit
interrupt occurs when the internal serial port shift register is loaded
with the data in the SPI/I2C transmit buffer SFR (SPI2CTx,
(SPI2CRx, Address 0x9B) is not read before new data is ready to
be loaded into the SPI/I 2 C receive buffer SFR (SPI2CRx,
Address 0x9B), an overflow condition has occurred. This
overflow condition, indicated by the SPIRxOF flag, forces the
new data to be discarded or overwritten if the RxOFW bit
(SPIMOD1, Address 0xE8) is set.
Address 0x9A) register. If the SPI master is in transmit
operating mode, and the SPI/I 2 C transmit buffer SFR (SPI2CTx,
Address 0x9A) register has not been written with new data by
the beginning of the next byte transfer, the transmit operation
SPITx
SPITxIRQ = 1
TRANSMIT SHIFT REGISTER
SPITx (EMPTY)
SPIRx
SPIRxIRQ = 1
RECEIVE SHIFT REGISTER
SPIRx (FULL)
stops.
STOPS TRANSFER IF TIMODE = 1
SPIRxOF = 1
When a new byte of data is received in the SPI/I C receive
2
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
buffer SFR (SPI2CRx, Address 0x9B), the SPI receive interrupt
flag is raised. If the data in the SPI/I 2 C receive buffer SFR
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL=0)
SS_b
Figure 111. SPI Receive and Transmit Interrupt and Status Flags
SPICPHA = 1
MISO
MOSI
SPIRx1 AND
SPITx1 FLAGS
SPIRx0 AND
SPITx0 FLAGS
? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MISO
MOSI
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
?
SPICPHA = 0
SPIRx1 AND
SPITx1 FLAGS
SPIRx0 AND
SPITx0 FLAGS
Figure 112. SPI Timing Configurations
Rev. B | Page 138 of 152
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