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参数资料
| 型号： | ADE7166ASTZF16 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 95/152页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 1PHASE 64LQFP |
| 标准包装： | 1 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
INTERRUPT FLAGS
The interrupt flags and status flags associated with the interrupt vectors are shown in Table 82 and Table 83. Most of the interrupts have
flags associated with them.
Table 82. Interrupt Flags
Interrupt Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
ITEMP (Temperature ADC) 1
IPSM (Power Supply)
IADE (Energy Measurement DSP)
Flag
TCON.1
TCON.5
TCON.3
TCON.7
SCON.1
SCON.0
T2CON.7
T2CON.6
N/A
IPSMF.6
MIRQSTL.7
Bit Name
IE0
TF0
IE1
TF1
TI
RI
TF2
EXF2
N/A
FPSM
ADEIRQFLAG
Description
External interrupt 0.
Timer 0.
External interrupt 1.
Timer 1.
Transmit interrupt.
Receive interrupt.
Timer 2 overflow flag.
Timer 2 external flag.
Temperature ADC interrupt. Does not have an interrupt flag associated with it.
PSM interrupt flag.
Read MIRQSTH, MIRQSTM, MIRQSTL.
1
This feature is not available in the ADE7116.
Table 83. Status Flags
Interrupt Source
ITEMP (Temperature ADC) 1
ISPI/I2CI
IRTC (RTC Interval Timer)
WDT (Watchdog Timer)
Flag
N/A
SPI2CSTAT
SPI2CSTAT
TIMECON.7
TIMECON.2
WDCON.2
Bit Address
N/A
N/A
N/A
MIDNIGHT
ALARM
WDS
Description
Temperature ADC interrupt. Does not have a status flag associated with it.
SPI interrupt status register.
I 2 C interrupt status register.
RTC midnight flag.
RTC alarm flag.
Watchdog timeout flag.
1
This feature is not available in the ADE7116.
A functional block diagram of the interrupt system is shown in
Figure 89. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external wake-up event occurs to wake the ADE7116/
ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 from PSM2
mode, a pending external interrupt is generated. When the EX0
bit (Bit 0) or the EX1 bit (Bit 2) in the interrupt enable SFR (IE,
Address 0xA8) is set to enable external interrupts, the program
counter is loaded with the IE0 or IE1 interrupt vector. The IE0
and IE1 interrupt flags (Bit 1 and Bit 3, respectively) in the
Timer/Counter 0 and Timer/Counter 1 control SFR (TCON,
Address 0x88) are not affected by events that occur when the
8052 MCU core is shut down during PSM2. See the Power
Supply Management (PSM) Interrupt section.
The RTC, temperature ADC, and I 2 C/SPI interrupts are latched
such that pending interrupts cannot be cleared without entering
their respective interrupt service routines. Clearing the RTC
interrupt. Similarly, clearing the I 2 C/SPI status bits in the SPI
Interrupt Status SFR (SPISTAT, Address 0xEA) does not cancel
a pending I 2 C/SPI interrupt. These interrupts remain pending
until the RTC or I 2 C/SPI interrupt vectors are enabled. Their
respective interrupt service routines are entered shortly
thereafter.
Figure 89 shows how the interrupts are cleared when the
interrupt service routines are entered. Some interrupts with
multiple interrupt sources are not automatically cleared;
specifically, the PSM, ADE, UART, and Timer 2 interrupt
vectors. Note that the INT0 and INT1 interrupts are only
cleared only if the external interrupt is configured to be
triggered by a falling edge by setting IT0 (Bit 0) in the
Timer/Counter 0 and Timer/Counter 1 control SFR (TCON,
Address 0x88). If INT0 or INT1 is configured to interrupt on a
low level, the interrupt service routine is reentered until the
respective pin goes high.
midnight flags and alarm flags does not clear a pending RTC
Rev. B | Page 95 of 152
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