参数资料
型号: ADE7166ASTZF16
厂商: Analog Devices Inc
文件页数: 50/152页
文件大小: 0K
描述: IC ENERGY METER 1PHASE 64LQFP
标准包装: 1
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
ANALOG-TO-DIGITAL CONVERSION
FILTER (RC)
SIGNAL
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 has two Σ-Δ analog-to-digital converters (ADCs). The
outputs of these ADCs are mapped directly to waveform sampling
SFRs (Address 0xE2 to Address 0xE7) and are used for energy
measurement internal digital signal processing. In PSM1 (battery
mode) and PSM2 (sleep mode), the ADCs are powered down to
minimize power consumption.
For simplicity, the block diagram in Figure 44 shows a first-
order Σ -Δ ADC. The converter is made up of the Σ -Δ modulator
and the digital low-pass filter (LPF).
A Σ -Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569, the sampling clock is equal to 4.096 MHz/5. The
1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal. If
the loop gain is high enough, the average value of the DAC
output (and, therefore, the bit stream) can approach that of the
input signal level.
For any given input value in a single sampling interval, the data
from the 1-bit ADC is virtually meaningless. Only when a large
number of samples are averaged is a meaningful result obtained.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
is 4.096 MHz/5 (819.2 kHz), and the band of interest is 40 Hz to
2 kHz. Oversampling has the effect of spreading the quantization
noise (noise due to sampling) over a wider bandwidth. With the
noise spread more thinly over a wider bandwidth, the quantiza-
tion noise in the band of interest is lowered (see Figure 43).
However, oversampling alone is not efficient enough to improve
the signal-to-noise ratio (SNR) in the band of interest. For example,
an oversampling ratio of four is required to increase the SNR by
only 6 dB (1 bit). To keep the oversampling ratio at a reasonable
level, it is possible to shape the quantization noise so that the
majority of the noise lies at the higher frequencies. In the Σ -Δ
modulator, the noise is shaped by the integrator, which has a
high-pass-type response for the quantization noise. The result is
that most of the noise is at the higher frequencies where it can
be removed by the digital LPF. This noise shaping is shown in
Figure 43.
ANTIALIAS
DIGITAL SAMPLING
FILTER FREQUENCY
SHAPED
NOISE
NOISE
This averaging is carried into the second part of the ADC, the
0
2
409.6
819.2
digital LPF. By averaging a large number of bits from the
FREQUENCY (kHz)
modulator, the low-pass filter can produce 24-bit data-words
that are proportional to the input signal level.
The Σ -Δ converter uses two techniques to achieve high
resolution from what is essentially a 1-bit conversion technique.
SIGNAL
NOISE
HIGH RESOLUTION
OUTPUT FROM DIGITAL
LPF
The first is oversampling. Oversampling means that the signal is
sampled at a rate (frequency) that is many times higher than the
0
2
409.6
FREQUENCY (kHz)
819.2
bandwidth of interest. For example, the sampling rate in the
MCLK/5
Figure 43. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
ANALOG
LOW-PASS FILTER
R
C
+
INTEGRATOR
LATCHED
COMPARATOR
DIGITAL
LOW-PASS
FILTER
24
V REF
... 10100101 ...
1-BIT DAC
Figure 44. First-Order Σ -? ADC
Rev. B | Page 50 of 1 5 2
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