参数资料
型号: ADE7754ARZ
厂商: Analog Devices Inc
文件页数: 4/44页
文件大小: 0K
描述: IC ENERGY METERING 3PHASE 24SOIC
标准包装: 31
输入阻抗: 370 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.8V
电流 - 电源: 7mA
电源电压: 4.75 V ~ 5.25 V
测量仪表类型: 3 相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 管件
产品目录页面: 797 (CN2011-ZH PDF)
配用: EVAL-ADE7754EBZ-ND - BOARD EVALAUTION FOR ADE7754

ADE7754
TIMING CHARACTERISTICS 1, 2
(AV DD = DV DD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz XTAL,
T MIN to T MAX = –40 C to +85 C, unless otherwise noted.)
Parameter
Spec
Unit
Test Conditions/Comments
Write Timing
t 1
t 2
t 3
t 4
t 5
t 6
t 7
t 8
50
50
50
10
5
400
50
100
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
CS Falling Edge to First SCLK Falling Edge
SCLK Logic High Pulsewidth
SCLK Logic Low Pulsewidth
Valid Data Setup Time before Falling Edge of SCLK
Data Hold Time after SCLK Falling Edge
Minimum Time between the End of Data Byte Transfers
Minimum Time between Byte Transfers during a Serial Write
CS Hold Time after SCLK Falling Edge
Read Timing
t 9 3
4
μ s (min)
Minimum Time between Read Command (i.e., a Write to Communication
Register) and Data Read
t 10
t 114
50
30
ns (min)
ns (min)
Minimum Time between Data Byte Transfers during a Multibyte Read
Data Access Time after SCLK Rising Edge following a Write to the
Communications Register
t 125
t 135
100
10
100
10
ns (max)
ns (min)
ns (max)
ns (min)
Bus Relinquish Time after Falling Edge of SCLK
Bus Relinquish Time after Rising Edge of CS
NOTES
1
Sample tested during initial release and after any redesign or process change
that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
200 A
I OL
2
3
4
5
See timing diagrams below and Serial Interface section of this data sheet.
Minimum time between read command and data read for all registers except
wavmode register, which is t 9 = 500 ns min.
Measured with the load circuit in Figure 1 and defined as the time required for
the output to cross 0.8 V or 2.4 V.
Derived from the measured time taken by the data outputs to change 0.5 V
TO
OUTPUT
PIN
C L
50pF
1.6mA
I OH
2.1V
when loaded with the circuit in Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF
Figure 1. Load Circuit for Timing Specifications
capacitor. The time quoted in the timing characteristics is the true bus relin-
quish time of the part and is independent of the bus loading.
t 8
CS
SCLK
t 1
t 2 t 3
t 4
t 5
t 7
t 7
t 6
DIN
1
0
A5
A4
A3
A2
A1
A0
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
Figure 2. Serial Write Timing
CS
t 1
SCLK
t 9
t 10
DIN
0
0
A5
A4
A3
A2
A1
A0
t 11
t 12
t 13
DOUT
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
Figure 3. Serial Read Timing
–4 –
LEAST SIGNIFICANT BYTE
REV. 0
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