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参数资料
| 型号： | ADM1041AARQZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Secondary-Side Controller with Current Share and Housekeeping |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO24 |
| 封装： | LEAD FREE, MO-137AE, QSOP-24 |
| 文件页数： | 44/56页 |
| 文件大小： | 991K |
| 代理商： | ADM1041AARQZ |
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ADM1041A
Bit No.
3–2
1
0
Rev. 0 | Page 44 of 56
Name
Soft Start
Address
Trim Lock
R/W
R/W
R/W
R/W
Description
Soft-Start Step
b3
0
0
1
1
EEPROM programmable second address bit.
When this bit is set, the trim registers including this register are not writable via SMBus. To
make registers writable again, the trim-lock bit in the EEPROM must first be erased and the
value downloaded using either power-up or test download.
Rise Time
300 μs
10 ms
20 ms
40 ms
b2
0
1
0
1
Table 26. Register 11h, Config5. Power-On Default from EEPROM Register 8111h During Power-Up
Bit No.
Name
R/W
Description
7
Current Limit Disable
R/W
Mask effect of OCP to general logic (status flag still gets asserted) when curr_lim_dis = 1.
6
PEN Polarity
R/W
Sets polarity of PEN output.
5
CBD Polarity
R/W
Sets polarity of CBD output.
4–3
Reserved
R/W
Don’t Care.
2
OCP Ridethrough
R/W
Set this bit to 1 when OCP ridethrough is required. A small delay still exists. Refer to Reg 12h.
1
GND_OK Disable
R/W
Disable GROUND_OK input to power management debounce logic.
0
CBD Latch Mode
R/W
Select CBD latch mode. 0 = nonlatching; 1 = latching.
Table 27. Register 12h, Config6. Power-On Default from EEPROM Register 8112h During Power-Up
Bit No.
Name
R/W
Description
7
Restart Mode
R/W
Restart mode (rsm). When rsm = 1, the circuit attempts to restart the supply after an
undervoltage or overcurrent at about 1-second intervals.
Latch mode. When rsm = 0, UV and OC faults latch the output off. Cycling PSON or removing
the supply to the IC is then required to reset the latch and permit a restart.
6
Micro AC OK
R/W
Configure microprocessor to control/gate signal from AC_IN_OK to AC_S_OK. See Table 43.
0 = Standalone.
1 = Microprocessor support mode.
5
Micro AC SENSE
R/W
Microproccessor control of AC
SENSE
. See Table 43.
4–3
OCP Ridethrough
R/W
OCP ridethrough (Reg 11h[2] = 0)
b4
b3
0
0
0
1
1
0
1
1
2
AC Sense Mode
R/W
AC
SENSE
mode. 0 means AC_OK is derived from AC
SENSE
1, whereas 1 means AC_OK is derived
from AC
SENSE
2.
1
Micro PS_ON
R/W
Microprocessor control of pson. See Table 43.
0
Current Share Clamp
R/W
0 = 75%. Set current share clamp release threshold.
1 = 88%.
OCP ridethrough (Reg11h[2] = 1)
b4
b3
0
0
0
1
1
0
1
1
Period
1 second
2 seconds
3 seconds
4 seconds
Period
128 μs
256 μs
384 μs
512 μs
Table 28. Register 13h, Config7. Power-On Default from EEPROM Register 8113h During Power-Up
Bit No.
Name
R/W
Description
7
PEN Polarity
R/W
Sets polarity of PEN output.
6
CBD Polarity
R/W
Sets polarity of CBD output.
5
DC_OK Polarity
R/W
Sets polarity of DC_OK output.
4
AC_OK Polarity
R/W
Sets polarity of AC_OK output.
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| ADM1041ARQ | 功能描述:IC PWR SUPP MON/LOAD SHAR 24QSOP RoHS:否 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ADM1041ARQ-2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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