参数资料
型号: ADM1069ACP
厂商: Analog Devices, Inc.
英文描述: SUPER SEQUENCER-TM WITH MARGINING CONTROL AND AUXILIARY ADC INPUTS
中文描述: 超时序与裕度控制以及辅助ADC输入商标
文件页数: 6/32页
文件大小: 626K
代理商: ADM1069ACP
ADM1069
Preliminary Technical Data
Parameter
DIGITAL INPUTS (VXn, A0, A1)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance
Programmable Pull-Down Current,
I
PULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Output Low Voltage, V
OL
2
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Bus Free Time, t
BUF
Start Setup Time, t
SU;STA
Start Hold Time, t
HD;STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
r
SCL, SDA Fall Time, t
f
Data Setup Time, t
SU;DAT
Data Hold Time, t
HD;DAT
Input Low Current, I
IL
SEQUENCING ENGINE TIMING
State Change Time
Rev. PrB | Page 6 of 32
Min
2.0
1
Typ
5
20
Max
0.8
1
Unit
V
V
μA
μA
pF
μA
Test Conditions/Comments
Maximum V
IN
= 5.5 V
Maximum V
IN
= 5.5 V
V
IN
= 5.5 V
V
IN
= 0
VDDCAP = 4.75, T
A
= 25°C, if known logic state is
required
I
OUT
= 3.0 mA
V
IN
= 0
2.0
4.7
4.7
4
4.7
4
250
5
10
0.8
0.4
400
1000
300
1
V
V
V
kHz
μs
μs
μs
μs
μs
μs
μs
ns
ns
μA
μs
1
At least one of the VH, VP1–3 pins must be
3.0 V to maintain the device supply on VDDCAP.
2
Specification is not production tested, but is supported by characterization data at initial product release.
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