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| 型号： | ADM1069AST-REEL7 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 电源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP32 |
| 封装： | MS-026-BBA, LQFP-32 |
| 文件页数： | 19/36页 |
| 文件大小： | 763K |
| 代理商： | ADM1069AST-REEL7 |
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ADM1069
Rev. A | Page 26 of 36
COMMUNICATING WITH THE ADM1069
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1069 (such as UV/OV
thresholds, glitch filter timeouts, and PDO configurations) is
dictated by the contents of RAM. The RAM is comprised of
digital latches that are local to each of the functions on the
device. The latches are double-buffered and have two identical
latches, Latch A and Latch B. Therefore, when an update to a
function occurs, the contents of Latch A are updated first, and
then the contents of Latch B are updated with identical data.
The advantages of this architecture are explained in detail in
this section.
The latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the
EEPROM (nonvolatile memory) to the local latches. This
download occurs in steps, as follows:
1.
With no power applied to the device, the PDOs are all high
impedance.
2.
When 1 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPn), the PDOs are all weakly
pulled to GND with a 20 kΩ impedance.
3.
When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
4.
The EEPROM downloads its contents to all Latch As.
5.
Once the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
6.
The first state definition is downloaded from EEPROM
into the SE 0.5 ms after the configuration download
completes.
Any attempt to communicate with the device prior to the
completion of the download causes the ADM1069 to issue a
no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
EEPROM into the RAM registers, the user could have to alter the
configuration of functions on the ADM1069, such as changing
the UV or OV limit of an SFD, changing the fault output of an
SFD, or adjusting the rise time delay of one of the PDOs.
The ADM1069 provides several options that allow the user to
update the configuration over the SMBus interface. The
following three options are controlled in the UPDCFG register.
Option 1
Update the configuration in real time. The user writes to RAM
across the SMBus and the configuration is updated immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1069 remains unchanged
and continues to operate in the original setup until the instruc-
tion is given to update the Latch Bs.
Option 3
Change EEPROM register contents without changing the RAM
contents, and then download the revised EEPROM contents to the
RAM registers. Again, with this method, the configuration of the
ADM1069 remains unchanged and continues to operate in the
original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents if
revisions to the configuration are unsatisfactory. For example, if
the user needs to alter an OV threshold, the RAM register can
be updated as described in Option 1. However, if the user is not
satisfied with the change and wants to revert to the original
programmed value, the device controller can issue a command
to download the EEPROM contents to the RAM again, as
described in Option 3, restoring the ADM1069 to its original
configuration.
The topology of the ADM1069 makes this type of operation
possible. The local, volatile registers (RAM) are all double-
buffered latches. Setting Bit 0 of the UPDCFG register to 1
leaves the double-buffered latches open at all times. If Bit 0 is set
to 0 and a RAM write occurs across the SMBus, only the first
side of the double-buffered latch is written to. The user must
then write a 1 to Bit 1 of the UPDCFG register. This generates a
pulse to update all the second latches at once. EEPROM writes
occur in a similar way.
The final bit in this register can enable or disable EEPROM
page erasure. If this bit is set high, the contents of an EEPROM
page can all be set to 1. If low, the contents of a page cannot be
erased, even if the command code for page erasure is pro-
grammed across the SMBus. The bit map for the UPDCFG
register is shown in the AN-721 Application Note. A flow chart
for download at power-up and subsequent configuration
updates is shown in Figure 34.
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