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参数资料
| 型号： | ADM1169ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 24/36页 |
| 文件大小： | 0K |
| 描述： | IC SEQUENCER/SUPERVISOR 40LFCSP |
| 标准包装： | 1 |
| 系列： | Super Sequencer® |
| 应用： | 电源监控器，序列发生器 |
| 输入电压： | 3 V ~ 14.4 V |
| 电源电压： | 3 V ~ 14.4 V |
| 电流 - 电源： | 4.2mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-WQ（6x6） |
| 包装： | 托盘 |
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ADM1169
To implement closed-loop margining,
Data Sheet
CHOOSING THE SIZE OF THE ATTENUATION
1.
2.
3.
4.
5.
6.
7.
Disable the four DACx outputs.
Set the DAC output voltage equal to the voltage on the
feedback node.
Enable the DAC.
Read the voltage at the dc-to-dc converter output that is
connected to one of the VPx, VH, or VXx pins.
If necessary, modify the DACx output code up or down to
adjust the dc-to-dc converter output voltage. Otherwise,
stop because the target voltage has been reached.
Set the DAC output voltage to a value that alters the supply
output by the required amount (for example, ±5%).
Repeat Step 4 through Step 6 until the measured supply
reaches the target voltage.
RESISTOR
The size of the attenuation resistor, R3, determines how much
the DAC voltage swing affects the output voltage of the dc-to-dc
Because the voltage at the feedback pin remains constant, the
current flowing from the feedback node to GND through R2 is
a constant. In addition, the feedback node itself is high impedance.
This means that the current flowing through R1 is the same as
the current flowing through R3. Therefore, a direct relationship
exists between the extra voltage drop across R1 during margining
and the voltage drop across R3.
This relationship is given by
Step 1 to Step 3 ensures that when the DACx output buffer is
turned on, it has little effect on the dc-to-dc converter output. The
Δ V OUT =
R1
R3
( V FB ? V DACOUT )
DAC output buffer is designed to power up without glitching by
first powering up the buffer to follow the pin voltage. It does not
drive out onto the pin at this time. When the output buffer is
properly enabled, the buffer input is switched over to the DAC,
and the output stage of the buffer is turned on. Output glitching
is negligible.
WRITING TO THE DACS
Four DAC ranges are offered. They can be placed with midcode
(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are
placed to correspond to the most common feedback voltages.
Centering the DAC outputs in this way provides the best use of
the DAC resolution. For most supplies, it is possible to place the
DAC midcode at the point where the dc-to-dc converter output
is not modified, thereby giving half of the DAC range to margin
up and the other half to margin down.
The DAC output voltage is set by the code written to the DACx
register. The voltage is linear with the unsigned binary number
in this register. Code 0x7F is placed at the midcode voltage, as
described previously. The output voltage is given by
DAC Output = ( DACx ? 0x7F)/255 × 0.6015 + V OFF
where V OFF is one of the four offset voltages.
There are 256 DAC settings available. The midcode value is
located at DAC Code 0x7F, as close as possible to the middle
of the 256 code range. The full output swing of the DACs is
+302 mV (+128 codes) and ?300 mV (?127 codes) around the
selected midcode voltage. The voltage range for each midcode
Table 10. Ranges for Midcode Voltages
where:
Δ V OUT is the change in V OUT .
V FB is the voltage at the feedback node of the dc-to-dc converter.
V DACOUT is the voltage output of the margining DAC.
This equation demonstrates that if the user wants the output
voltage to change by ±300 mV, then R1 = R3. If the user wants
the output voltage to change by ±600 mV, R1 = 2 × R3, and so on.
It is best to use the full DAC output range to margin a supply.
Choosing the attenuation resistor in this way provides the most
resolution from the DAC, meaning that with one DAC code
change, the smallest effect on the dc-to-dc converter output
voltage is induced. If the resistor is sized up to use a code such
as 27 decimal to 227 decimal to move the dc-to-dc converter
output by ±5%, it takes 100 codes to move 5% (each code moves
the output by 0.05%). This is beyond the readback accuracy of
the ADC, but it should not prevent the user from building a
circuit to use the most resolution.
DAC LIMITING AND OTHER SAFETY FEATURES
Limit registers (called DPLIMx and DNLIMx) on the device
offer the user some protection from firmware bugs that can
cause catastrophic board problems by forcing supplies beyond
their allowable output ranges. Essentially, the DAC code written
into the DACx register is clipped such that the code used to set
the DAC voltage is given by
DAC Code
= DACx, DACx ≥ DNLIMx and DACx ≤ DPLIMx
= DNLIMx, DACx < DNLIMx
= DPLIMx, DACx > DPLIMx
In addition, the DAC output buffer is three-stated if DNLIMx >
Midcode
Voltage (V)
0.6
0.8
1.0
1.25
Minimum Voltage
Output (V)
0.300
0.500
0.700
0.950
Maximum Voltage
Output (V)
0.902
1.102
1.302
1.552
DPLIMx. By programming the limit registers this way, the user
can make it very difficult for the DAC output buffers to be turned
on during normal system operation. The limit registers are among
the registers downloaded from EEPROM at startup.
Rev. A | Page 24 of 36
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