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| 型号： | ADM1169ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/36页 |
| 文件大小： | 0K |
| 描述： | IC SEQUENCER/SUPERVISOR 40LFCSP |
| 标准包装： | 1 |
| 系列： | Super Sequencer® |
| 应用： | 电源监控器，序列发生器 |
| 输入电压： | 3 V ~ 14.4 V |
| 电源电压： | 3 V ~ 14.4 V |
| 电流 - 电源： | 4.2mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-WQ（6x6） |
| 包装： | 托盘 |
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ADM1169
If none of the states are set as fault record trigger states, then the
black box is considered disabled, and read/write access is allowed
without having to halt the black box fault recorder.
SERIAL BUS INTERFACE
The ADM1169 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device,
under the control of a master device. It takes approximately
1 ms after power-up for the ADM1169 to download from its
EEPROM. Therefore, access to the ADM1169 is restricted until
the download is complete.
Identifying the ADM1169 on the SMBus
The device is powered up with a default serial bus address. The
five MSBs of the address are set to 10011; the two LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1169 s to one SMBus.
Data Sheet
The general SMBus protocol operates in the following three steps.
Step 1
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data line SDA,
while the serial clock line SCL remains high. This indicates that
a data stream follows. All slave peripherals connected to the serial
bus respond to the start condition and shift in the next eight bits,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low period
before the ninth clock pulse, known as the acknowledge bit, and
by holding it low during the high period of this clock pulse.
All other devices on the bus remain idle while the selected device
Table 11. Serial Bus Slave Address
A1 Pin A0 Pin Hex Address
Low Low 0x98
7-Bit Address 1
1001100x
waits for data to be read from or written to it. If the R/W bit is a 0,
the master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Low
High
High
High
Low
High
0x9A
0x9C
0x9E
1001101x
1001110x
1001111x
Step 2
Data is sent over the serial bus in sequences of nine clock pulses:
eight bits of data followed by an acknowledge bit from the slave
1
x = read/write bit. The address is shown only as the first seven MSBs.
device. Data transitions on the data line must occur during the
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 12 lists these registers
with their values and functions.
Table 12. Identification Register Values and Functions
low period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
may be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
Name
MANID
REVID
MARK1
MARK2
Address
0xF4
0xF5
0xF6
0xF7
Value
0x41
0x10
0x00
0x00
Function
Manufacturer ID for Analog Devices
Silicon revision
Software brand
Software brand
It may be an instruction telling the slave device to expect a block
write, or it may be a register address that tells the slave where
subsequent data is to be written. Because data can flow in only
one direction, as defined by the R/W bit, sending a command to
a slave device during a read operation is not possible. Before a read
General SMBus Timing
read and write operations using the SMBus. The SMBus specification
defines specific conditions for different types of read and write
operations, which are discussed in the Write Operations and
Read Operations sections.
operation, it may be necessary to perform a write operation to tell
the slave what sort of read operation to expect and/or the address
from which data is to be read.
Step 3
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line high
during the 10 th clock pulse to assert a stop condition. In read
mode, the master device releases the SDA line during the low
period before the ninth clock pulse, but the slave device does not
pull it low. This is known as a no acknowledge. The master then
takes the data line low during the low period before the 10 th clock
pulse and then high during the 10 th clock pulse to assert a stop
condition.
Rev. A | Page 28 of 36
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