参数资料
型号: ADM1176-2ARMZ-R7
厂商: Analog Devices Inc
文件页数: 15/24页
文件大小: 0K
描述: IC CTRLR HOTSWAP 16.5V 10-MSOP
产品培训模块: Hot Swap Design
标准包装: 1
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: 3.15 V ~ 16.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 标准包装
产品目录页面: 792 (CN2011-ZH PDF)
配用: EVAL-ADM1176EBZ-ND - BOARD EVALUATION FOR ADM1176
其它名称: ADM1176-2ARMZ-R7DKR
Data Sheet
ADM1176
When the initial timing cycle terminates, the device is ready to
(1)
(2)
(3)(4)
(5)(6)
(7)
start a hot swap operation (assuming that the ON pin is asserted).
In the example shown in Figure 30, the ON pin is asserted at the
same time that V CC is applied; therefore, the hot swap operation
starts immediately after Time Point 4. At this point, the FET
gate is charged up with a 12.5 μA current source.
At Time Point 5, the threshold voltage of the FET is reached,
and the load current begins to flow. The FET is controlled to
keep the sense voltage at 100 mV (this corresponds to a
maximum load current level defined by the value of RSENSE).
At Time Point 6, V GATE and V OUT have reached their full
potential, and the load current has settled to its nominal level.
Figure 31 illustrates the situation where the ON pin is asserted
after V CC is applied.
V CC
V ON
V TIMER
V GATE
V SENSE
(1)
(2)
(3)(4) (5)
(6)
V OUT
V CC
INITIAL TIMING
CYCLE
Figure 31. Startup (ON Asserts After Power Is Applied)
V ON
V TIMER
V GATE
V SENSE
V OUT
INITIAL TIMING
CYCLE
HOT SWAP RETRY ON THE ADM1176-1
With the ADM1176-1, the device turns off the FET after an
overcurrent fault and then uses the TIMER pin to time a delay
before automatically retrying to hot swap.
As with all ADM1176 devices, an overcurrent fault is timed by
charging the TIMER capacitor with a 60 μA pull-up current.
When the TIMER pin reaches 1.3 V, the fault current limit time
has been reached, and the GATE pin is pulled down. On the
ADM1176-1, the TIMER pin is then pulled down with a 2 μA
current sink. When the TIMER pin reaches 0.2 V, it automati-
cally restarts the hot swap operation.
The cooldown period is related to C TIMER by Equation 8.
Figure 30. Startup (ON Asserts as Power Is Applied)
t COOL ≈ 550 × C TIMER ms/μF
Therefore, the retry duty cycle is as given by Equation 9.
t FAULT / ( t COOL + t FAULT ) × 100% = 3.8%
Rev. C | Page 15 of 24
(8)
(9)
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