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参数资料
| 型号： | ADN2526ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC LASER DRIVER 11.3GBPS 16LFCSP |
| 标准包装： | 1,500 |
| 类型： | 激光二极管驱动器 |
| 数据速率： | 11.3Gbps |
| 通道数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 46mA |
| 电流 - 调制： | 80mA |
| 电流 - 偏置： | 100mA |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
ADN2526
THEORY OF OPERATION
Data Sheet
As shown in Figure 1, the ADN2526 consists of an input stage
and two voltage-controlled current sources for bias and modula-
tion. The bias current, which is available at the IBIAS pin, is
controlled by the voltage applied at the BSET pin and can be
50?
50?
C
C
ADN2526
DATAP
DATAN
monitored at the IBMON pin. The differential modulation
current, which is available at the IMODP and IMODN pins, is
controlled by the voltage applied to the MSET pin. The output
stage implements the active back-match circuitry for proper
transmission line matching and power consumption reduction.
The ADN2526 can drive a load having differential resistance
ranging from 5 ? to 50 ?. The excellent back-termination in
the ADN2526 absorbs the signal reflections from the TOSA
end, enabling excellent optical eye quality, even though the
TOSA is significantly misterminated.
DATA SIGNAL SOURCE
Figure 18. AC-Coupling the Data Source to the ADN2526 Data Inputs
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
INPUT STAGE
The input stage of the ADN2526 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
BSET
ADN2526
800?
R
VCC
R
I BMON
IBMON
IBIAS
VCC
I BIAS
DATAP
50?
VCC
200?
200?
2?
GND
Figure 19. Voltage-to-Current Converter Used to Generate IBIAS
The voltage-to-current conversion factor is set at 100 mA/V by
50?
DATAN
Figure 17. Equivalent Circuit of the Input Stage
The DATAP and DATAN pins are terminated internally with a
100 ? differential termination resistor. This minimizes signal
reflections at the input, which can otherwise lead to degradation in
the output eye diagram. It is not recommended to drive the
ADN2526 with single-ended data signal sources.
The ADN2526 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the common-
mode voltages of the data signal source and the input stage of
the driver (see Figure 18). The ac-coupling capacitors should
have an impedance much less than 50 ? over the required
the internal resistors, and the bias current is monitored using a
current mirror with a gain equal to 1/100. By connecting a 1 k?
resistor between IBMON and VEE, the bias current can be moni-
tored as a voltage across the resistor. A low temperature coefficient
precision resistor must be used for the IBMON resistor (R IBMON ).
Any error in the value of R IBMON that is due to tolerances or to drift
in its value over temperature contributes to the overall error
budget for the IBIAS monitor voltage. If the IBMON voltage is
connected to an ADC for analog-to-digital conversion, R IBMON
should be placed close to the ADC to minimize errors due to
voltage drops on the ground plane.
The equivalent circuits of the BSET, IBIAS, and IBMON pins
VCC
VCC
frequency range. Generally, this is achieved using 10 nF to 100 nF
capacitors.
BSET
800?
In SFP+ MSA applications, the DATAP and DATAN pins need
to be connected to the SFP+ connector directly. This connection
requires enhanced ESD protection to support the SFP+ module
hot plug-in application.
Rev. B | Page 10 of 16
200?
Figure 20. Equivalent Circuit of the BSET Pin
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