参数资料
型号: ADN2804ACPZ-RL7
厂商: Analog Devices Inc
文件页数: 5/24页
文件大小: 0K
描述: IC CLK/DATA REC 622MBPS 32-LFCSP
标准包装: 1,500
类型: 时钟和数据恢复(CDR),多路复用器
PLL:
主要目的: SONET/SDH
输入: CML
输出: LVDS
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 是/是
频率 - 最大: 622MHz
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘,CSP
供应商设备封装: 32-LFCSP-VQ(5x5)
包装: 带卷 (TR)
Data Sheet
ADN2804
Rev. C | Page 13 of 24
JITTER SPECIFICATIONS
The ADN2804 CDR is designed to achieve the best bit-
error-rate (BER) performance and to exceed the jitter
transfer, generation, and tolerance specifications proposed
for SONET/SDH equipment defined in the Telcordia
Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2804 performance with respect to those specifications.
Jitter Generation
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For SONET devices, the jitter generated
must be less than 0.01 UI rms and less than 0.1 UI p-p.
Jitter Transfer
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal vs. the frequency.
This parameter measures the amount of jitter on an input signal
that can be transferred to the output signal (see Figure 15). This
amount is limited.
0.1
ACCEPTABLE
RANGE
fC
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
JI
TTE
R
GA
IN
(
d
B
)
0
5
801-
015
Figure 15. Jitter Transfer Curve
Jitter Tolerance
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see Figure 16).
15.00
1.50
0.15
f0
f1
f2
f3
f4
JITTER FREQUENCY (kHz)
SLOPE = –20dB/DECADE
IN
P
U
T
J
ITT
E
R
AM
P
L
IT
UD
E
(
U
I
p
-p
)
0
58
01
-0
16
Figure 16. SONET Jitter Tolerance Mask
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