参数资料
型号: ADN2855ACPZ-R7
厂商: Analog Devices Inc
文件页数: 3/20页
文件大小: 0K
描述: IC CLK/RECOVERY MULTI 32LFCSP
标准包装: 1,500
类型: 时钟和数据恢复(CDR)
PLL:
主要目的: GPON,BPON,GEPON
输入: CML
输出: LVDS
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 是/是
频率 - 最大: 200MHz
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘,CSP
供应商设备封装: 32-LFCSP-VQ(5x5)
包装: 带卷 (TR)
ADN2855
Rev. A | Page 11 of 20
THEORY OF OPERATION
The ADN2855 is designed specifically for burst mode data
recovery in GPON/BPON/GEPON optical line terminal (OLT)
receivers.
The ADN2855 requires a reference clock that is frequency locked
to the incoming data. The FLL (frequency-locked loop) of the
ADN2855 acquires frequency lock with respect to this reference
clock, pulling the VCO towards 0 ppm frequency error. It is
assumed that the upstream bursts to the OLT are clocked by the
recovered clock from the optical network terminal (ONT) CDR.
This guarantees frequency lock to the OLT system clock.
The ADN2855 has a preamble detector that looks for a maximum
transition density pattern (1010…) within the preamble. Once
this pattern is detected in the preamble, the on-chip delay/phase-
locked loop (D/PLL) quickly acquires phase lock to the incoming
burst within 12 UI of the 1010… pattern. The D/PLL also pulls
in any remaining frequency error that was not pulled in by the
FLL. The incoming data is retimed by the recovered clock and
output either serially or in a 4-bit parallel output nibble.
The ADN2855 requires a RESET signal between bursts to set
the device into a fast phase acquisition mode. The RESET signal
must be asserted within 8 UI of the end of the previous burst,
and it must be deasserted prior to the start of the maximum
transition density portion of the preamble, which is specifically
provided for the burst mode clock recovery device to acquire
the phase of the incoming burst. The RESET signal must be at
least 16 UI wide. See the Reset Timing Options section for more
details.
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