参数资料
| 型号： | ADN4605ABPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/56页 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SWITCH 352BGA |
| 标准包装： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉点开关 |
| 电路： | 1 x 40:40 |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 2.25 V ~ 3.6 V |
| 电流 - 电源： | 55mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 352-LBGA 裸露焊盘 |
| 供应商设备封装： | 352-BGA-EP（35x35） |
| 包装： | 托盘 |
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Data Sheet
ADN4605
Rev. A | Page 35 of 56
SPI SERIAL CONTROL INTERFACE
The SPI serial interface of the ADN4605 consists of four wires:
CS, SCK, SDI, and SDO. In order to access the SPI interface the
SER/PAR line must be held at logic high and the I2C/SPI line
must be held at logic low. The CS pin is used to select the device
when more than one device is connected to the serial clock and
data lines and must be held at logic low to enable write/read
capability to the device when in SPI control mode.
The SCK is used to clock data in and out of the part. The SDI
line is used to write to the registers, and the SDO line is used to
read data back from the registers. Data on SDI line is clocked on
the rising edge of SCK. Data on SDO changes on the falling
edge of SCK. The recommended pull-up resistor value is
between 500 and 1 k. Strong pull-ups are needed when
serial clock speeds that are close to the maximum limit are used
or when the SPI interface lines are experiencing large capacitive
loading. Larger resistor values can be used for pull-up resistors
when the serial clock speed is reduced.
The part operates in a slave mode and requires an externally
applied serial clock to the SCK input. The serial interface is
designed to allow the part to be interfaced to systems that
provide a serial clock that is synchronized to the serial data.
There are two types of serial operations, a read and a write.
Command words are used to distinguish between a read and a
write operation as shown in Table 18.
Table 18. SPI Command Words
Write Command
0x02 (0000 0010)
Read Command
0x03 (0000 0011)
Write Operation
Figure 48 shows the diagram for a write operation to the
ADN4605. Data is clocked into the registers on the rising edge
of SCK. When the CS line is high, the SDI and SDO lines are in
three-state mode. Only when the CS goes from a high to a low
does the part accept any data on the SDI line. The 8-bit write
command must precede the register address byte. The register
address byte is then followed by the data byte as shown in
To allow continuous writes, the address pointer register auto-
increments by one without having to load the address pointer
register each time. Subsequent data bytes are written into
sequential registers. Note that not all registers in the 256-byte
address space exist and not all registers are writable. Zeroes
should be entered for nonexistent address fields when imple-
menting a continuous write operation. Address space 0xE0 to
Address 0xFF is reserved and should not be overwritten.
Read Operation
To read back from a register, first send the read command
followed by the desired register address. Subsequent clock
cycles, with CS asserted low, stream data starting from the
desired register address onto SDO, MSB first. SDO changes on
the falling edge of SCK. Multiple data reads are possible in SPI
interface mode because the address pointer register is auto-
incremented.
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