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| 型号： | ADP1048DC1-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 40/84页 |
| 文件大小： | 0K |
| 描述： | DAUGHTERCARD ADP1048 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，功率因数校正 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADP1048 |
| 次要属性： | USB，I2C接口 |
| 已供物品： | 板 |
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ADP1047/ADP1048
SAVING REGISTER SETTINGS INTO EEPROM
The register settings cannot be saved to the factory scratch pad
located in Page 0 of the EEPROM main block. This is to prevent
the user from accidentally overriding the factory trim settings
Data Sheet
EEPROM CRC CHECKSUM
As a simple method of checking that the values downloaded
from EEPROM and the internal registers are consistent, a CRC
checksum is implemented.
and default register settings.
Save Register Settings to the User Scratch Pad
The register settings can be saved to the user scratch pad located in
Page 1 of the EEPROM main block using the STORE_USER_ALL
command (Command Code 0x15). Before this command can be
executed, the EEPROM must first be unlocked for writing (see
?
?
When the data from the internal registers is saved to the
EEPROM (Page 1 of the main block), the total number
of 1s from all the registers is counted and written into the
EEPROM as the last byte of information. This is called
the CRC checksum.
When the data is downloaded from the EEPROM into the
the Unlock EEPROM section).
After the register settings are saved to the user scratch pad,
any subsequent power cycle automatically downloads the latest
stored user information from the EEPROM into the internal
registers.
Note that execution of the STORE_USER_ALL command
automatically performs a page erase to Page 1 of the EEPROM
main block, after which the registers are stored in EEPROM.
Therefore, it is important to wait at least 35 ms for the operation
to complete before executing the next PMBus command.
internal registers, a similar counter that sums all 1s from
the values loaded into the registers is saved. This value is
compared with the CRC checksum from the previous
upload operation.
If the values match, the download operation was successful. If
the values differ, the EEPROM download operation failed, and
the EEPROM_CRC fault flag is set (Register 0xFE81, Bit 5).
To read the EEPROM CRC checksum value, execute the
EEPROM_CRC_CHKSUM command (Register 0xD1). This
command returns the CRC checksum accumulated in the
counter during the download operation.
Note that the CRC checksum is an 8-bit cyclical accumulator
that wraps around to 0 when 255 is reached.
Rev. 0 | Page 40 of 84
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