参数资料
型号: ADP1621ARMZ-R7
厂商: Analog Devices Inc
文件页数: 12/32页
文件大小: 0K
描述: IC REG CTRLR PWM CM 10-MSOP
标准包装: 1
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 97%
电源电压: 2.9 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 标准包装
产品目录页面: 791 (CN2011-ZH PDF)
配用: ADP1621-EVALZ-ND - BOARD EVALUATION FOR ADP1621
其它名称: ADP1621ARMZ-R7DKR

V OUT
V IN
ADP1621
THEORY OF OPERATION
The ADP1621 is a fixed-frequency, current-mode, step-up dc/dc
converter controller. It drives an external n-channel MOSFET
to step the input voltage up to a higher output voltage. It can be
used for SEPIC, flyback, boost, buck-boost, forward, and other
converter topologies. It operates at a fixed switching frequency that
is set by an external resistor over a range of 100 kHz to 1.5 MHz,
and it can be synchronized to an external clock by connecting
the SDSN pin to the clock.
The input supply current to the ADP1621 is less than 3 mA
during normal operation and less than 10 μA during shutdown.
The ADP1621 can drive large external MOSFETs, allowing it to
support load currents in excess of 10 A.
CONTROL LOOP
The ADP1621 uses a current-mode architecture to regulate the
output voltage. The output voltage is monitored at FB through
a resistive voltage divider. The voltage at FB is compared to the
internal 1.215 V reference voltage by the internal transconductance
error amplifier to create an error current at COMP. A resistor-
capacitor compensation impedance connected from COMP to
GND converts the error current to an error voltage.
At the beginning of the switching cycle, the MOSFET is turned
Data Sheet
CURRENT-SENSE CONFIGURATIONS
The ADP1621 can sense the current across the on resistance of
the MOSFET to minimize external component count and improve
efficiency by eliminating the power that would be lost in a current-
sense resistor. This lossless technique eliminates the need for an
expensive current-sense resistor. In the lossless mode configuration,
the voltage at the CS pin (or the switch-node voltage at the drain of
the MOSFET) must not exceed 30 V (see Figure 28). This technique
maximizes efficiency and reduces cost. In practice, when the
calculated V SW approaches 30 V, one should build the board and
measure the actual V SW before committing to the lossless mode
design. Because of the parasitic inductance in the diode, output
capacitor, and PCB traces, V SW typically has narrow peaks that
exceed the theoretical maximum voltage at V SW —the sum of
V OUT and the forward-voltage drop of Diode D1. If the measured
peak voltage exceeds 30 V, or if a more accurate current limit is
desired, then the CS pin can be connected to an external current-
sense resistor in the source of the MOSFET (Figure 29). The
maximum power output is limited by the selection of the
external components.
L D1
on and the inductor current ramps up. The MOSFET current is
measured and converted to a voltage using R CS or R DSON and is
added to the stabilizing slope-compensation ramp. The resulting
voltage sum passes through the current-sense amplifier to generate
PIN IN
CS
ADP1621
SDSN
R S
V SW
C O
the current-sense voltage. When the current-sense voltage is
GATE
greater than the COMP error voltage, the MOSFET is turned off
and the inductor current ramps down until the internal clock
initiates the next switching cycle. The duty-cycle of the PWM
PGND
GND
modulator is thus adjusted to provide the necessary load current
at the desired output voltage. Because the output voltage ultimately
Figure 28. CS Pin Connection for V SW < 30 V, Lossless Mode
(No Current-Sense Resistor Needed)
controls the peak inductor current through the COMP error
V IN
L V SW D1
V OUT
voltage, this scheme is referred to as peak current-mode control.
With light loads, the converter can also operate under discon-
PIN
IN
tinuous conduction mode and pulse-skipping modulation to
maintain output-voltage regulation. These two forms of operation
are discussed in detail in the Light Load Operation section.
Note that the converter can also be designed to operate in
discontinuous conduction mode at full load if desired.
GATE
ADP1621
SDSN
CS
PGND GND
R S
R CS
C O
Overall, the current-mode regulation system of the ADP1621
allows fast transient responses while maintaining a stable output
voltage. By selecting the proper resistor-capacitor network from
COMP to GND, the regulator response can be optimized for a
wide range of input voltages, output voltages, and load currents.
Rev. B | Page 12 of 32
Figure 29. CS Pin Connection for V SW > 30 V, Resistor Sense Mode
with a Current-Sense Resistor, R CS
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