参数资料
型号: ADP1621ARMZ-R7
厂商: Analog Devices Inc
文件页数: 4/32页
文件大小: 0K
描述: IC REG CTRLR PWM CM 10-MSOP
标准包装: 1
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1.5MHz
占空比: 97%
电源电压: 2.9 V ~ 5.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 标准包装
产品目录页面: 791 (CN2011-ZH PDF)
配用: ADP1621-EVALZ-ND - BOARD EVALUATION FOR ADP1621
其它名称: ADP1621ARMZ-R7DKR
ADP1621
Data Sheet
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
GATE DRIVER
GATE Rise Time 9
GATE Fall Time 9
t R
t F
C GATE = 3.3 nF
C GATE = 3.3 nF
17
13
ns
ns
1
2
3
4
5
6
7
8
9
The maximum input voltage is the shunt regulation voltage, which is typically 5.5 V and can range from 5.3 V to 6.0 V over the specified temperature range.
The ADP1621 is tested in a feedback servo loop, which servos V FB to the internal reference voltage. The voltage change in FB is measured while V IN is changed from
2.9 V to 5 V. The line regulation is calculated by (?V FB /V FB ) × 100%/?V IN .
The ADP1621 is tested in a feedback servo loop, which servos V FB to the internal reference voltage, and V COMP is forced from 1.4 V to 1.5 V. The V COMP range is
(1.0 V ≤ V COMP ≤ 2.0 V).
The peak slope-compensation current at the CS pin is typically 70 μA, and effectively clamped at 116 mV. Thus, R S should not exceed 1.6 k? (116 mV/70 μA).
Guaranteed by design for thermal shutdown. When the thermal junction temperature of the ADP1621 reaches approximately 150°C, the ADP1621 goes into thermal
shutdown and the GATE voltage is pulled low. When the junction temperature drops below about 140°C, the soft start sequence is initiated and the ADP1621 resumes
normal operation.
f OSC is the natural oscillation frequency, f SYNC is the synchronization frequency, and f SW is the switching frequency. If synchronization is used, then f SW = f SYNC ; otherwise, f SW = f OSC .
Guaranteed by design and bench characterization.
To ensure proper synchronization operation, set the synchronization frequency, f SYNC , to 1.2× of the free-running frequency, f OSC . Although the switching frequency can
be synchronized to as high as 1.8 MHz, the peak slope-compensation current decreases at higher synchronization frequencies. It is recommended that the maximum
f SYNC be less than 1.4× of f OSC and should not exceed 1.8 MHz. The slope-compensation resistor, R S , should be chosen for the synchronization frequency (see the Slope
Compensation section in the Application Information: Boost Converter section).
GATE rise and fall times are measured from 10% to 90% levels.
Rev. B | Page 4 of 32
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