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| 型号： | ADP1828ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/36页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 20LFCSP |
| 标准包装： | 1,500 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 720kHz |
| 占空比： | 93% |
| 电源电压： | 3 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 20-WFQFN 裸露焊盘，CSP |
| 包装： | 带卷 (TR) |
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ADP1828
Depending on component selection, one zero might already be
generated by the ESR of the output capacitor. Calculate this zero
corner frequency, f ESR , as
Note that if the converter is being synchronized, the ramp
voltage, V RAMP , is lower than 1.0 V by the percentage of
frequency increase over the nominal setting of the FREQ pin:
V RAMP = 1 . 0 V ? ? FREQ ? ?
f ESR =
1
2 π R ESR C OUT
(18)
? f ?
? f SYNC ?
(22)
The gain of the LC filter at crossover can be linearly
approximated from Figure 37 as
A FILTER = A LC + A ESR
For example, if FREQ is grounded or connected to VREG, then
f FREQ is 300 kHz or 600 kHz, respectively. If the frequency is set
by a resistor, then f FREQ is 300 kHz and f SYNC is the frequency set
by the resistor. V RAMP is greater than 1.0 V if f SYNC is less than
f FREQ . The rest of the system gain needs to reach 0 dB at cross-
A FILTER = ? 40 dB × log ? ? ESR
? ? 20 dB × log ? CO
? f
?
? ESR
?
?
? f
? f LC
? ? f
?
?
?
(19)
over. The total gain of the system, therefore, is given by
A T = A MOD + A FILTER + A COMP
(23)
If f ESR ≈ f CO , then add another 3 dB to account for the local
difference between the exact solution and the linear approxi-
mation in Equation 19.
where:
A MOD is the gain of the PWM modulator.
A FILTER is the gain of the LC filter including the effects of
the ESR zero.
A COMP is the gain of the compensated error amplifier.
GAIN
0dB
f LC
f ESR
f CO
f SW
FREQUENCY
Additionally, the phase of the system must be brought back
up to guarantee stability. Note from the Bode plot of the filter
that the LC contributes ?180° of phase shift (see Figure 37).
–40dB/dec
Because the error amplifier is an integrator at low frequency,
it contributes an initial ?90°. Therefore, before adding com-
pensation or accounting for the ESR zero, the system is already
down ?270°. To avoid loop inversion at crossover, or ?180°
PHASE
0°
–20dB/dec
A FILTER
phase shift, a good initial practical design is to require a phase
margin of 60°, which is therefore an overall phase loss of ?120°
from the initial low frequency dc phase. The goal of the com-
pensation is to boost the phase back up from ?270° to ?120°
at crossover.
Two common compensation schemes are used, which are
sometimes referred to as Type II or Type III compensation,
depending on whether the compensation design includes
–90°
Φ FILTER
–180°
Figure 37. LC Filter Bode Plot
To compensate the control loop, the gain of the system must
be brought back up so that it is 0 dB at the desired crossover
frequency. Some gain is provided by the PWM modulation itself.
Compensator sections). Dominant-pole compensation, or
single-pole compensation, is referred to as Type I compensation,
but it is not very useful for dealing successfully with switching
regulators.
If the zero produced by the ESR of the output capacitor provides
sufficient phase boost at crossover, Type II compensation is
adequate. If the phase boost produced by the ESR of the output
capacitor is not sufficient, another zero is added to the compen-
sation network, and thus Type III is used.
? V IN
? V
?
?
A MOD
= 20 log ?
? RAMP
?
?
(20)
In Figure 38, the location of the ESR zero corner frequency
gives a significantly different net phase at the crossover
frequency.
For systems using the internal oscillator, this becomes
A MOD = 20 log ?
? 1 . 0 V ?
?
? V IN ?
? ?
(21)
Rev. C | Page 22 of 36
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP1828-BL1-EVZ | 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1828 - Boxed Product (Development Kits) |
| ADP1828-BL2-EVZ | 制造商:Analog Devices 功能描述:BLANK ADISIMPOWER EVAL ADP1828 - Boxed Product (Development Kits) |
| ADP1828HC-EVALZ | 功能描述:BOARD EVALUATION ADP1828HC RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ADP1828LC-EVALZ | 功能描述:BOARD EVALUATION ADP1828LC RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ADP1828YRQZ-R7 | 功能描述:IC REG CTRLR BUCK PWM VM 20-QSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
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