参数资料
型号: ADP1828ACPZ-R7
厂商: Analog Devices Inc
文件页数: 26/36页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 20LFCSP
标准包装: 1,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 720kHz
占空比: 93%
电源电压: 3 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 20-WFQFN 裸露焊盘,CSP
包装: 带卷 (TR)
ADP1828
COMP
FB
V OUT
R TOP
R BOT
1
EN FOR BOTH ADP1828
V OUT_MASTER
ERROR
AMPLIFIER
TRK
0.6V
SS
R TRKT
MASTER
VOLTAGE
V OUT_SLAVE
TRK_SLAVE
DETAIL VIEW OF
ADP1828
R TRKB
4
Figure 42. Voltage Tracking
CH1 5.00V
BW
CH2 1.00V
BW
M 100ms
A CH1
2.60V
COINCIDENT TRACKING
The most common application is coincident tracking, used
in core vs. I/O voltage sequencing and similar applications.
Coincident tracking limits the slave output voltage to be the
same as the master voltage until it reaches regulation. Connect
the slave TRK input to a resistor divider from the master voltage
that is the same as the divider used on the slave FB pin. This
forces the slave voltage to be the same as the master voltage.
For coincident tracking, use the following equation:
R TRKT = R TOP and R TRKB = R BOT
where:
R TOP and R BOT are the values chosen in the Compensating the
See Figure 43 for an example of a coincident tracking circuit.
CH3 1.00V BW CH4 1.00V
Figure 45. Coincident Tracking of Figure 43
As the master voltage rises, the slave voltage also rises in the
same pattern. Eventually, the slave voltage reaches its regulation
voltage, where the internal reference takes over the regulation
while the TRK input continues to increase and thus removes
itself from influencing the output voltage. To ensure that the
output voltage accuracy is not compromised by the TRK pin
being too close in voltage to the 0.6 V reference, make sure
that the final value of the master voltage is greater than the
slave regulation voltage by at least 10%, or 60 mV as seen at the
FB node (the higher, the better). A difference of 60 mV between
TRK and the 0.6 V reference produces about 3 mV of offset in
the error amplifier, or 0.5%, at room temperature, while 100 mV
between them produces only 0.6 mV or 0.1% offset. For accurate
tracking, set the final voltage at TRK to less than or equal to
EN
SS
C SS
1μF
ADP1828
OR
ADP1829
FB
3.3V
V OUT_MASTER
R TRKT
20k ?
1.1V
R TRKB
10k ?
EN
ADP1828
TRK
FB
SS
1.8V
V OUT_SLAVE
R TOP
20k ?
R BOT
10k ?
0.5 V. However, this condition would trip the PGOOD signal.
RATIOMETRIC TRACKING
Ratiometric tracking limits the output voltage to a fraction of
the master voltage. For example, the termination voltage for
DDR memories (VTT) is set to half the VDDQ voltage.
MASTER VOLTAGE
C SS
150nF
SLAVE VOLTAGE
Figure 43. Example of a Coincident Tracking Circuit
TIME
MASTER VOLTAGE
SLAVE VOLTAGE
TIME
Figure 44. Coincident Tracking
Figure 46. Ratiometric Tracking
For ratiometric tracking, the simplest configuration is to tie the
TRK pin of the slave channel to the FB pin of the master channel.
The advantage of this is having the fewest components, but the
accuracy suffers as the TRK pin voltage becomes equal to the
internal reference voltage and an offset is imposed on the error
amplifier of about ?18 mV at room temperature.
Rev. C | Page 26 of 36
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