参数资料
型号: ADP1828ACPZ-R7
厂商: Analog Devices Inc
文件页数: 27/36页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 20LFCSP
标准包装: 1,500
PWM 型: 电压模式
输出数: 1
频率 - 最大: 720kHz
占空比: 93%
电源电压: 3 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 20-WFQFN 裸露焊盘,CSP
包装: 带卷 (TR)
ADP1828
A more accurate solution is to provide a divider from the
master voltage that sets the TRK pin voltage to be something
lower than 0.6 V at regulation, for example, 0.5 V. The slave
channel can be viewed as having a 0.5 V external reference
supplied by the master voltage. Keep in mind that PGOOD
Figure 49 shows an example of DDR memory termination
application circuit, where the DDR memory termination voltage,
VTT, is ? of VDDQ. VTT can sink current during the off cycle
of the ADP1828. The output waveform in Figure 50 shows that
VTT changes by one-half of the output change in VDDQ.
is tripped when the TRK voltage is set to less than 0.55 V.
Once this is complete, the FB divider for the slave voltage is
EN
2.5V
VDDQ
EN
1.25V
VTT
? 1 + TOP ?
R BOT ? ?
?
= ?
? 1 + TRKT ?
R TRKB ? ?
?
TRK
R TRKB
designed as in the Compensating the Voltage Mode Buck
Regulator section except to substitute the 0.5 V reference
for the V FB voltage. The ratio of the slave output voltage to
the master voltage is a function of the two dividers:
? R ?
V OUT
V MASTER ? R ?
?
(51)
C SS
1μF
SS
ADP1828 ADP1828
OR
ADP1829
R TRKT
40.2k ?
0.5V
FB
FB
SS
10k ?
C SS
150nF
Figure 49. An Example of a DDR Termination Circuit
T
R TOP
15k ?
R BOT
10k ?
Figure 47 shows an example of ratiometric tracking circuit and
TRK
Figure 48 shows its voltage tracking waveforms.
VDDQ (2.5V ± 0.25V, AC-COUPLED)
EN
SS
C SS
1μF
ADP1828
OR
ADP1829
FB
3.3V
V OUT_MASTER
R TRKT
49.9k ?
0.55V
R TRKB
10k ?
EN
ADP1828
TRK
FB
SS
1.8V
V OUT_SLAVE
R TOP
22.6k ?
R BOT
10k ?
1
3
2
VTT (1.25V ± 0.125V, AC-COUPLED)
C SS
150nF
CH1 500mV
BW CH2
100mV
BW
M 200μs
A CH1
50.0mV
1
Figure 47. An Example of a Ratiometric Tracking Circuit
EN FOR BOTH ADP1828
V OUT_MASTER
V OUT_SLAVE
CH3 500mV BW
Figure 50. DDR Termination; Output Waveforms of Figure 49
In addition, by selecting the resistor values in the divider carefully,
Equation 51 shows that the slave voltage output can be made to
have a faster ramp rate than that of the master voltage by setting
the TRK voltage at the slave larger than 0.6 V and R TRKB greater
than R TRKT . Make sure that the master SS period is long enough
(that is, use a sufficiently large SS capacitor) such that the input
inrush current does not run into the current limit of the power
supply during startup.
EN FOR BOTH ADP1828
TRK_SLAVE
4
1
CH1 5.00V
BW
CH2 1.00V
BW
M 100ms
A CH1
2.60V
V OUT_MASTER
CH3 1.00V
BW
CH4 1.00V
Figure 48. Ratiometric Tracking of Figure 47
Another option is to add another tap to the divider for the
master voltage. Split the R BOT resistor of the master voltage into
two pieces, with the new tap at 0.5 V when the master voltage is
in regulation. This saves one resistor, but be aware that Type III
4
TRK_SLAVE
V OUT_SLAVE
compensation on the master voltage causes the feedforward
signal of the master voltage to appear at the TRK input of the
CH1 5.00V
CH3 1.00V
BW
BW
CH2 1.00V
CH4 1.00V
BW
M 100ms
A CH1
2.60V
slave channel.
Rev. C | Page 27 of 36
Figure 51. Ratiometric Tracking of Figure 47 with R TRKT = 5 kΩ
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