参数资料
型号: ADP3207CJCPZ-RL
厂商: ON Semiconductor
文件页数: 14/32页
文件大小: 0K
描述: IC CTLR SYNC BUCK 7BIT 40-LFCSP
标准包装: 2,500
应用: 控制器,Intel IMVP-6
输入电压: 3.3 V ~ 22 V
输出数: 3
输出电压: 0.3 V ~ 1.5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-VQ(6x6)
包装: 带卷 (TR)
ADP3207C
Theory of Operation
The ADP3207C combines a multi ? mode Ramp Pulse
Modulated (PWM/RPM) control with multi ? phase logic
outputs for use in 1 ? , 2 ? , and 3 ? phase synchronous buck CPU
core supply power converters. The internal 7 ? bit VID DAC
conforms to Intel IMVP ? 6 specifications. Multi ? phase
operation is important for producing the high currents and
low voltages demanded by today’s microprocessors.
Handling high currents in a single ? phase converter puts high
thermal stress on the system components, such as the
inductors and MOSFETs.
The multi ? mode control of the ADP3207C ensures a stable
high performance topology for:
? Balancing currents and thermals between phases
? High speed response at the lowest possible switching
frequency and minimal output decoupling
? Minimizing thermal switching losses due to lower
frequency operation
? Tight load line regulation and accuracy
? High current output by supporting up to 3 ? phase
operation
? Reduced output ripple due to multi ? phase ripple
cancellation
? High power conversion efficiency both at heavy load
and light load
? PC board layout noise immunity
? Ease of use and design due to independent component
selection
? Flexibility in operation by allowing optimization of
design for low cost or high performance
Number of Phases
The number of operational phases and their phase
relationship is determined by internal circuitry that monitors
the PWM outputs. Normally, the ADP3207C operates as a
3 ? phase controller. For 2 ? phase operation, the PWM3 pin is
connected to V CC 5.0 V programs, and for 1 ? phase
operation, the PWM3 and PWM2 pins are connected to V CC
5.0 V programs.
When the ADP3207C is initially enabled, the controller
sinks 50 m A on the PWM2 and PWM3 pins. An internal
comparator checks the voltage of each pin against a high
threshold of 3.0 V. If the pin voltage is high due to pullup to
the V CC 5.0 V rail, then the phase is disabled. The phase
detection is made during the first three clock cycles of the
internal oscillator. After phase detection, the 50 m A current
sink is removed. The pins that are not connected to the V CC
5.0 V rail function as normal PWM outputs. The pins that are
connected to V CC enter into high impedance state.
The PWM outputs are 5.0 V logic ? level signals intended
for driving external gate drivers, such as the ADP3611.
Because each phase is monitored independently, operation
approaching 100% duty cycle is possible. In addition, more
than one output can operate at a time to allow overlapping
phases.
Operation Modes
For the ADP3207C, the number of phases can be selected
by the user as described in the Number of Phases section, or
they can dynamically change based on system signals to
optimize the power conversion efficiency at heavy and light
CPU loads.
During a VID transient or at a heavy load condition,
indicated by DPRSLP going low and PSI going high, the
ADP3207C runs in full ? phase mode. All user ? selected
phases operate in interleaved PWM mode, which results in
minimal VCore ripple and best transient performance.
While in light load mode, indicated by either PSI going low
or DPRSLP going high, only Phase 1 of the ADP3207C is
in operation to maximize power conversion efficiency.
In addition to the change of phase number, the ADP3207C
dynamically changes operation modes. In multi ? phase
operation, the ADP3207C runs in PWM mode, with
switching frequency controlled by the master clock. In
single ? phase mode based on the PSI signal, the ADP3207C
switches to RPM mode, where the switching frequency is no
longer controlled by the master clock, but by the ripple
voltage appearing on the COMP pin. The PWM1 pin is set
to high each time the COMP pin voltage rises to a limit
determined by the VID voltage and programmed by the
external resistor connected between Pin VRPM and
Pin RRPM. In single ? phase mode based on the DPRSLP
signal, the ADP3207C runs in RPM mode, with the
synchronous rectifier (low ? side) MOSFETs of Phase 1
being controlled by the DCM pin to prevent any reverse
inductor current. Thus, the switch frequency varies with the
load current, resulting in maximum power conversion
efficiency in deeper sleep mode of CPU operation. In
addition, during any VID transient, system transient
(entry/exit of deeper sleep), or current limit, the ADP3207C
goes into full phase mode, regardless of DPRSLP and PSI
signals, eliminating current stress to Phase 1.
Table 1 summarizes how the ADP3207C dynamically
changes phase number and operation modes based on
system signals and operating conditions.
http://onsemi.com
14
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