参数资料
型号: ADP3207CJCPZ-RL
厂商: ON Semiconductor
文件页数: 27/32页
文件大小: 0K
描述: IC CTLR SYNC BUCK 7BIT 40-LFCSP
标准包装: 2,500
应用: 控制器,Intel IMVP-6
输入电压: 3.3 V ~ 22 V
输出数: 3
输出电压: 0.3 V ~ 1.5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-VQ(6x6)
包装: 带卷 (TR)
ADP3207C
1 *
(eq. 21)
X
SW
O
R LIM +
ramp size that gives an optimal balance for good stability,
transient response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds
to the internal ramp to produce the following overall ramp
signal at the PWM input:
V R
V RT +
2 (1 * n D)
n f C R
For this example, the overall ramp signal is found to be 2.2 V.
Setting the Switching Frequency for RPM Mode Operation
of Phase.
During the RPM mode operation of Phase 1, the
ADP3207C runs in pseudo constant frequency, given that
the load current is high enough for continuous current mode.
While in discontinuous current mode, the switching
frequency is reduced with the load current in a linear
manner. When considering power conversion efficiency in
light load, lower switching frequency is usually preferred
for RPM mode. However, the VCore ripple specification in
the IMVP ? 6 sets the limitation for lowest switching
frequency. Therefore, depending on the inductor and output
capacitors, the switching frequency in RPM mode can be
equal, larger, or smaller than its counterpart in PWM mode.
A resistor from RPM to GND sets the pseudo constant
frequency as following:
Where:
R MON is the current monitor resistor. R MON is connected
from I MON pin to FBRTN.
R LIM is the current limit resistor.
R O is the output load line resistance.
I FS is the output current when the voltage on I MON is at full
scale.
Current Limit Setpoint
To select the current limit setpoint, we need to find the
resistor value for R LIM . The current limit threshold for the
ADP3207C is set when the current in R LIM is equal to the
internal reference current of 20 m A. The current in R LIM is
equal to the inductor current times R O . R LIM can be found
using the following equation:
I LIM R O
20 m A (eq. 25)
Where:
R LIM is the current limit resistor. R LIM is connected from the
I LIM pin to ground.
R O is the output load line resistance.
I LIM is the current limit set point. This is the peak inductor
current that will trip current limit.
In this example, if choosing 55 A for I LIM , R LIM is
5.775 k W , which is close to a standard 1% resistance of
5.76 k W .
The per phase current limit described earlier has its limit
determined by the following:
R T
R RPM +
2
V VID ) 1.0 V
A R
R R
(1 * D)
C R
V VID
f SW
I PHLIM ^
V COMP(MAX) * V R * V BIAS
A D R DS(MAX)
)
I R
2
(eq. 26)
R RPM +
V R
D LIM + D MIN
R LIM
R MON +
R O
I FS
* 0.5 k W (eq. 22)
Where:
A R is the internal ramp amplifier gain.
C R is the internal ramp capacitor value.
R R is an external resistor on the RAMPADJ pin to set the
internal ramp magnitude.
Because R R = 280 k W , the following resistance sets up
300 kHz switching frequency in RPM operation:
2 280 k W 0.5  (1 * 0.061)  1.150
1.150 V ) 1.0 V 462 k W 5 pF 300 kHz
* 5 W + 202 k W (eq. 23)
Output Current Monitor
The ADP3207C has output current monitor. The I MON pin
sources a current proportional to the total inductor current.
A resistor, R MON , from I MON to FBRTN sets the gain of the
output current monitor. A 0.1 m F is placed in parallel with
R MON to filter the inductor current ripple and high frequency
load transients. Since the I MON pin is connected directly to
the CPU, it is clamped to prevent it from going above 1.15 V.
The I MON pin current is equal to the R LIM times a fixed
gain of 10. R MON can be found using the following equation:
1.15 V
10 (eq. 24)
For the ADP3207C, the maximum COMP voltage
(V COMP(MAX) ) is 3.3 V, the COMP pin bias voltage (V BIAS )
is 1.0 V, and the current balancing amplifier gain (A D ) is 5.
Using a V R of 0.55 V, and a R DS(MAX) of 3.8 m W (low ? side
on ? resistance at 150 ° C) results in a per phase limit of 85 A.
Although this number seems high, this current level can only
be reached with a absolute short at the output and the current
limit latchoff function shutting down the regulator before
overheating occurs.
This limit can be adjusted by changing the ramp voltage
V R . However, users should not set the per phase limit lower
than the average per phase current (I LIM /n).
There is also a per phase initial duty ? cycle limit at
maximum input voltage:
V COMP(MAX) * V BIAS
(eq. 27)
For this example, the duty ? cycle limit at maximum input
voltage is found to be 0.25 when D is 0.061.
Feedback Loop Compensation Design
Optimized compensation of the ADP3207C allows the best
possible response of the regulator’s output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an output
http://onsemi.com
27
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