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参数资料
| 型号： | ADP5585ACBZ-00-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/40页 |
| 文件大小： | 0K |
| 描述： | IC PORT EXPANDER 10I/O 16WLSCP |
| 标准包装： | 1 |
| 应用： | 小键盘输入，输入/输出扩展 |
| 接口： | I²C |
| 封装/外壳： | 16-UFBGA，WLCSP |
| 供应商设备封装： | 16-WLCSP（1.59x1.59） |
| 包装： | 标准包装 |
| 安装类型： | 表面贴装 |
| 其它名称： | ADP5585ACBZ-00-R7DKR |
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Data Sheet
ADP5585
Rev. C | Page 31 of 40
RESET1_EVENT_B Register 0x2A
Table 50. RESET1_EVENT_B Bit Descriptions
Bit(s)
Bit Name
Access
Description
7
RESET1_EVENT_B_LEVEL
Read/write
Defines which level the second reset event should be to generate the RESET1
signal. Refer to Table 49.
6 to 0
RESET1_EVENT_B[6:0]
Read/write
Defines an event that can be used to generate the RESET1 signal. Refer to Table 11.
RESET1_EVENT_C Register 0x2B
Table 51. RESET1_EVENT_C Bit Descriptions
Bit(s)
Bit Name
Access
Description
7
RESET1_EVENT_C_LEVEL
Read/write
Defines which level the second reset event should be to generate the RESET1
signal. Refer to Table 49.
6 to 0
RESET1_EVENT_C[6:0]
Read/write
Defines an event that can be used to generate the RESET1 signal. Refer to Table 11.
RESET2_EVENT_A Register 0x2C
Table 52. RESET2_EVENT_A Bit Descriptions
Bit(s)
Bit Name
Access
Description
7
RESET2_EVENT_A_LEVEL
Read/write
Defines which level the first reset event should be to generate the RESET2 signal.
For key events, use the following settings:
0 = not applicable; releases not used for reset generation.
1 = press is used as reset event.
For GPIs and logic outputs configured for FIFO updates, use the following settings:
0 = inactive event used as reset condition.
1 = active event used as reset condition.
6 to 0
RESET2_EVENT_A[6:0]
Read/write
Defines an event that can be used to generate the RESET2 signal. Up to two events
can be defined for generating the RESET2 signal, using RESET2_EVENT_A[6:0], and
RESET2_EVENT_B[6:0]. If one of the registers is 0, that register is not used for reset
generation. All reset events must be detected at the same time to trigger the reset.
RESET2_EVENT_B Register 0x2D
Table 53. RESET2_EVENT_B Bit Descriptions
Bit(s)
Bit Name
Access
Description
7
RESET2_EVENT_B_LEVEL
Read/write
Defines which level the second reset event should be to generate the RESET2
signal. Refer to Table 52.
6 to 0
RESET2_EVENT_B[6:0]
Read/write
Defines an event that can be used to generate the RESET2 signal. Refer to Table 11.
RESET_CFG Register 0x2E
Table 54. RESET_CFG Bit Descriptions
Bit(s)
Bit Name
Access
Description
7
RESET2_POL
Read/write
Sets the polarity of RESET2.
0 = RESET2 is active low.
1 = RESET2 is active high.
6
RESET1_POL
Read/write
Sets the polarity of RESET1.
0 = RESET1 is active low.
1 = RESET1 is active high.
5
RST_PASSTHRU_EN
Read/write
Allows the RST pin to override (OR with) the RESET1signal. This function not
applicable to RESET2.
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| ADP5585ACBZ-01-R7 | 功能描述:IC PORT EXPANDER 10I/O 16WLSCP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| ADP5585ACBZ-02-R7 | 功能描述:IC PORT EXPANDER 10I/O 16WLSCP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| ADP5585ACBZ-04-R7 | 制造商:AD 制造商全称:Analog Devices 功能描述:Keypad Decoder and I/O Expansion |
| ADP5585ACPZ-00-R7 | 功能描述:IC PORT EXPANDER 10I/O 16LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:* 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| ADP5585ACPZ-01-R7 | 功能描述:IC PORT EXPANDER 10I/O 16LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:* 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
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