参数资料
型号: ADP7104ARDZ-3.3-R7
厂商: Analog Devices Inc
文件页数: 17/28页
文件大小: 0K
描述: IC REG LDO 3.3V .5A 8SOIC
标准包装: 1,000
稳压器拓扑结构: 正,固定式
输出电压: 3.3V
输入电压: 最高 20V
电压 - 压降(标准): 0.35V @ 500mA
稳压器数量: 1
电流 - 输出: 500mA(最小值)
电流 - 限制(最小): 625mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm Width)裸露焊盘
供应商设备封装: 8-SOIC-EP
包装: 带卷 (TR)

Data Sheet
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP7104 is designed for operation with small, space-saving
ceramic capacitors but functions with most commonly used
capacitors as long as care is taken with regard to the effective series
resistance (ESR) value. The ESR of the output capacitor affects the
stability of the LDO control loop. A minimum of 1 μF capacitance
with an ESR of 1 ? or less is recommended to ensure the stability
of the ADP7104 . Transient response to changes in load current is
also affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP7104 to
large changes in load current. Figure 62 shows the transient
responses for an output capacitance value of 1 μF.
LOAD CURRENT
1
ADP7104
Figure 63 depicts the capacitance vs. voltage bias characteristic
of an 0402, 1 μF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is ~±15% over the ?40°C to +85°C temperature
range and is not a function of package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
VOLTAGE (V)
2
OUTPUT VOLTAGE
Figure 63. Capacitance vs. Voltage Characteristic
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.
CH1 500mA ?
CH2 50mV
M 20μs
A CH1
270mA
C EFF = C BIAS × (1 ? TEMPCO ) × (1 ? TOL )
(1)
T 10%
Figure 62. Output Transient Response, V OUT = 1.8 V, C OUT = 1 μF
Input Bypass Capacitor
Connecting a 1 μF capacitor from VIN to GND reduces
the circuit sensitivity to printed circuit board (PCB) layout,
especially when long input traces or high source impedance
are encountered. If greater than 1 μF of output capacitance is
required, the input capacitor should be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP7104 , as long as they meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manufac-
tured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over
the necessary temperature range and dc bias conditions. X5R
or X7R dielectrics with a voltage rating of 6.3 V to 25 V are
where:
C BIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
over ?40°C to +85°C is assumed to be 15% for an X5R dielectric.
The tolerance of the capacitor (TOL) is assumed to be 10%, and
C BIAS is 0.94 μF at 1.8 V, as shown in Figure 63.
Substituting these values in Equation 1 yields
C EFF = 0.94 μF × (1 ? 0.15) × (1 ? 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO overtemper-
ature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP7104 , it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
recommended. Y5V and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.
Rev. F | Page 17 of 28
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