参数资料
| 型号： | ADP7104ARDZ-3.3-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/28页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3.3V .5A 8SOIC |
| 标准包装： | 1,000 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3.3V |
| 输入电压： | 最高 20V |
| 电压 - 压降（标准）： | 0.35V @ 500mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 500mA（最小值） |
| 电流 - 限制（最小）： | 625mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 供应商设备封装： | 8-SOIC-EP |
| 包装： | 带卷 (TR) |
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Data Sheet
POWER-GOOD FEATURE
The ADP7104 provides a power-good pin (PG) to indicate
the status of the output. This open-drain output requires an
external pull-up resistor to VIN. If the part is in shutdown
mode, current-limit mode, or thermal shutdown, or if it falls
below 90% of the nominal output voltage, the power-good pin
(PG) immediately transitions low. During soft-start, the rising
threshold of the power-good signal is 93.5% of the nominal
output voltage.
The open-drain output is held low when the ADP7104 has suffi-
cient input voltage to turn on the internal PG transistor. The PG
transistor is terminated via a pull-up resistor to VOUT or VIN.
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90% trip point when
this voltage is falling. Regulator input voltage brownouts or
glitches trigger power no good signals if V OUT falls below 90%.
A normal power-down causes the power-good signal to go low
when V OUT drops below 90%.
falling threshold over temperature.
ADP7104
NOISE REDUCTION OF THE ADJUSTABLE ADP7104
The ultralow output noise of the fixed output ADP7104 is
achieved by keeping the LDO error amplifier in unity gain
and setting the reference voltage equal to the output voltage.
This architecture does not work for an adjustable output
voltage LDO. The adjustable output ADP7104 uses the more
conventional architecture where the reference voltage is fixed
and the error amplifier gain is a function of the output voltage.
The disadvantage of the conventional LDO architecture is that
the output voltage noise is proportional to the output voltage.
The adjustable LDO circuit may be modified slightly to reduce
the output voltage noise to levels close to that of the fixed
output ADP7104 . The circuit shown in Figure 69 adds two
additional components to the output voltage setting resistor
divider. C NR and R NR are added in parallel with R FB1 to reduce
the ac gain of the error amplifier. R NR is chosen to be equal to
R FB2 , this limits the ac gain of the error amplifier to approxi-
mately 6 dB. The actual gain is the parallel combination of R NR
and R FB1 divided by R FB2 . This ensures that the error amplifier
always operates at greater than unity gain.
C NR is chosen by setting the reactance of C NR equal to R FB1 ?
6
5
PG
PG
PG
PG
PG
–40°C
–5°C
+25°C
+85°C
+125°C
R NR at a frequency between 50 Hz and 100 Hz. This sets the
frequency where the ac gain of the error amplifier is 3 dB
down from its dc gain.
4
V IN = 8V
CIN +
1μF
VIN
VOUT
ADJ
R FB1
40.2k ?
+ C NR
100nF
V OUT = 5V
+ COUT
1μF
3
2
OFF
ON
R1
100k ?
R2
100k ?
EN/
UVLO
GND
PG
R FB2
13k ?
R NR
13k ?
RPG
100k ?
PG
1
5
15 μV × 1 + ? ?
? / 13 k ? ?
? ? ? ?
? ? 1 / 13 k ? + 1 / 40 . 2 k ? ?
0
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0
V OUT (V)
Figure 67. Typical Power-Good Threshold vs. Temperature, V OUT Rising
6
PG –40°C
PG –5°C
PG +25°C
PG +85°C
PG +125°C
4
3
Figure 69. Noise Reduction Modification to Adjustable LDO
The noise of the adjustable LDO is can be found by using the
formula below assuming the noise of a fixed output LDO is
approximately 15 μV.
1
? ? ? ?
?
Based on the component values shown in Figure 69, the
ADP7104 has the following characteristics:
? DC gain of 4.09 (12.2 dB)
2
1
?
?
?
?
3 dB roll off frequency of 59 Hz
High frequency ac gain of 1.76 (4.89 dB)
Noise reduction factor of 1.33 (2.59 dB)
RMS noise of the adjustable LDO without noise reduction
0
4.2
4.3
4.4
4.5
4.6
V OUT (V)
4.7
4.8
4.9
5.0
?
of 27.8 μV rms
RMS noise of the adjustable LDO with noise reduction
Figure 68. Typical Power-Good Threshold vs. Temperature, V OUT Falling
Rev. F | Page 19 of 28
(assuming 15 μV rms for fixed voltage option) of
19.95 μV rms
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| ADP7104ARDZ-5.0-R7 | 功能描述:IC REG LDO 5V .5A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:800 系列:- 稳压器拓扑结构:正，固定式 输出电压:2.5V 输入电压:最高 16V 电压 - 压降（标准）:0.7V @ 4A 稳压器数量:1 电流 - 输出:4A 电流 - 限制（最小）:4.2A 工作温度:0°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-6，D²Pak（5 引线+接片），TO-263BA 供应商设备封装:TO-263-5 包装:带卷 (TR) 其它名称:AP1184K525L-13AP1184K525LDITR |
| ADP7104ARDZ-9.0-R7 | 功能描述:IC REG LDO 9V .5A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:800 系列:- 稳压器拓扑结构:正，固定式 输出电压:2.5V 输入电压:最高 16V 电压 - 压降（标准）:0.7V @ 4A 稳压器数量:1 电流 - 输出:4A 电流 - 限制（最小）:4.2A 工作温度:0°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-6，D²Pak（5 引线+接片），TO-263BA 供应商设备封装:TO-263-5 包装:带卷 (TR) 其它名称:AP1184K525L-13AP1184K525LDITR |
| ADP7104ARDZ-R7 | 功能描述:IC REG LDO ADJ .5A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 标准包装:800 系列:- 稳压器拓扑结构:正，固定式 输出电压:2.5V 输入电压:最高 16V 电压 - 压降（标准）:0.7V @ 4A 稳压器数量:1 电流 - 输出:4A 电流 - 限制（最小）:4.2A 工作温度:0°C ~ 125°C 安装类型:表面贴装 封装/外壳:TO-263-6，D²Pak（5 引线+接片），TO-263BA 供应商设备封装:TO-263-5 包装:带卷 (TR) 其它名称:AP1184K525L-13AP1184K525LDITR |
| ADP7104CP-EVAL | 制造商:Analog Devices 功能描述:EVAL LDO 20V0.3ALFCSPADP7102 制造商:Analog Devices 功能描述:ADP7104, LDO, CMOS, EVALUATION BOARD |
| ADP7104CP-EVALZ | 制造商:Analog Devices 功能描述: |
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