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| 型号： | ADP8863ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/52页 |
| 文件大小： | 0K |
| 描述： | IC LED DRVR WHIT BCKLGT 20-WLCSP |
| 标准包装： | 1 |
| 拓扑： | 切换式电容器（充电泵） |
| 输出数： | 7 |
| 内部驱动器： | 是 |
| 类型 - 主要： | 背光，LED 闪烁器 |
| 类型 - 次要： | RGB，白色 LED |
| 频率： | 800kHz ~ 1.32MHz |
| 电源电压： | 2.5 V ~ 5.5 V |
| 输出电压： | 4.3 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-UFBGA，WLCSP |
| 供应商设备封装： | 20-WLCSP |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 85°C |
| 其它名称： | ADP8863ACPZ-R7DKR |
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ADP8863
POWER STAGE
Because typical white LEDs require up to 4 V to drive them,
some form of boosting is required over the typical variation in
battery voltage. The ADP8863 accomplishes this with a high
efficiency charge pump capable of producing a maximum I OUT
of 240 mA over the entire input voltage range (2.5 V to 5.5 V).
Charge pumps use the basic principle that a capacitor stores
charge based on the voltage applied to it, as shown in the
following equation:
in parallel and are discharged to V OUT in parallel. In certain fault
modes, the switches are opened and the output is physically
isolated from the input.
Automatic Gain Selection
Each LED that is driven requires a current source. The voltage
on this current source must be greater than a minimum head-
room voltage (200 mV typical) to maintain accurate current
regulation. The gain is automatically selected based on the
minimum voltage (V DX ) at all of the current sources. At startup,
Q = C × V
(1)
the device is placed into G = 1× mode and the output charges
By charging the capacitors in different configurations, the
charge, and therefore the gain, can be optimized to deliver the
voltage required to power the LEDs. Because a fixed charging
and discharging combination must be used, only certain
multiples of gain are available. The ADP8863 is capable of
automatically optimizing the gain (G) from 1×, 1.5×, and 2×.
These gains are accomplished with two capacitors (labeled C1
and C2 in Figure 26) and an internal switching network.
In G = 1× mode, the switches are configured to pass VIN
directly to VOUT. In this mode, several switches are connected
in parallel to minimize the resistive drop from input to output.
In G = 1.5× and 2× modes, the switches alternatively charge
from the battery and discharge into the output. For G = 1.5×,
the capacitors are charged from V IN in series and are discharged to
V OUT in parallel. For G = 2×, the capacitors are charged from V IN
to V IN . If any V DX level is less than the required headroom
(200 mV), the gain is increased to the next step (G = 1.5×).
A 100 μs delay is allowed for the output to stabilize prior to
the next gain switching decision. If there remains insufficient
current sink headroom, then the gain is increased again to 2×.
Conversely, to optimize efficiency, it is not desirable for the
output voltage to be too high. Therefore, the gain reduces when
the headroom voltage is great enough. This point (labeled
V DMAX in Figure 27) is internally calculated to ensure that the
lower gain still results in ample headroom for all the current
sinks. The entire cycle is illustrated in Figure 27.
Note that the gain selection criteria apply only to active current
sources. If current sources have been deactivated through an
I 2 C command (for example, only five LEDs are used), then the
voltages on the deactivated current sources are ignored.
STANDBY
EXIT STANDBY
STARTUP:
CHARGE
V IN TO V OUT
0
1
EXIT
STARTUP
VOU T > V OUT(START)
0
G=1
1
WAIT
100μs (TYP)
MIN (V D1:D7 ) < V HR(UP)
1
G = 1.5
WAIT
100μs (TYP)
MIN (V D1:D7 ) < V HR(UP)
0
0
MIN (V D1:D7 ) > V DMAX
1
0
1
G=2
WAIT
100μs (TYP)
MIN (V D1:D7 ) < V DMAX
NOTES
1. V DMAX IS THE CALCULATED GAIN DOWN TRANSITION POINT.
Figure 27. State Diagram for Automatic Gain Selection
Rev. A | Page 12 of 52
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