参数资料
型号: ADS62P44IRGCT
厂商: Texas Instruments
文件页数: 19/78页
文件大小: 0K
描述: IC ADC 14BIT DUAL 105MSPS 64VQFN
产品培训模块: Data Converter Basics
标准包装: 1
位数: 14
采样率(每秒): 105M
数据接口: 串行,并联
转换器数目: 2
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘
供应商设备封装: 64-VQFN 裸露焊盘(9x9)
包装: 标准包装
输入数目和类型: 2 个差分,单极
其它名称: 296-23137-6
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
Table 17.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
<OFFSET TC>
<GAIN CORRECTION>
1A
<LOW LATENCY>
Offset correction time constant
0 to 0.5 dB, steps of 0.05 dB
D2
–D0
0000
0 dB gain, default after reset
0001
+0.5 dB gain
0010
+0.10 dB gain
0011
+0.15 dB gain
0100
+0.20 dB gain
0101
+0.25 dB gain
0110
+0.30 dB gain
0111
+0.35 dB gain
1000
+0.40 dB gain
1001
+0.45 dB gain
1010
+0.5 dB gain
D6-D4
<OFFSET TC> Time constant of offset correction in number of clock cycles (seconds, for sampling frequency = 125
MSPS)
000
227 (1.1 s)
001
226 (0.55 s)
010
225 (0.27 s)
011
224 (0.13 s)
100
228 (2.15 s)
101
229 (4.3 s)
110
227 (1.1 s)
111
227 (1.1 s)
D7
<LOW LATENCY>
0
Default latency, 14 clock cycles
1
Low latency enabled, 10 clock cycles
– Digital Processing Block is bypassed.
Table 18.
A7
–A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
<FILTER COEFF
<OFFSET Enable>
SELECT
>
<FILTER Enable>
<DECIMATION RATE>
<ODD TAP
1B
Offset correction
0
Enable
>
In-built or custom
Enable digital filtering
Decimate by 2,4,8
enable
coefficients
26
Copyright
2007–2012, Texas Instruments Incorporated
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