参数资料
型号: ADS62P44IRGCT
厂商: Texas Instruments
文件页数: 58/78页
文件大小: 0K
描述: IC ADC 14BIT DUAL 105MSPS 64VQFN
产品培训模块: Data Converter Basics
标准包装: 1
位数: 14
采样率(每秒): 105M
数据接口: 串行,并联
转换器数目: 2
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘
供应商设备封装: 64-VQFN 裸露焊盘(9x9)
包装: 标准包装
输入数目和类型: 2 个差分,单极
其它名称: 296-23137-6
0
14 Bits
Filter Select
CLIPPER
From
ADC
Output
Tooutputbuffers
LVDSorCMOS
DECIMATION
BY 2/4/8
Bypass
Filter
Bypass
Decimation
24 TAP FILTER
- LOWPASS
-HIGHPASS
- BANDPASS
DIGITAL
FILTERandDECIMATION
DIGITAL PROCESSINGBLOCK
GAIN
CORRECTION
FINEGAIN
OFFSET
CORRECTION
GainCorrection
(0.05dBSteps)
FineGain
(0to6dB
0.05dBSteps)
14 Bits
14Bits
Disable
Offset
Correction
FreezeOffset
Correction
OFFSET
ESTIMATION
BLOCK
B0289-01
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
DETAILS OF DIGITAL PROCESSING BLOCK
Figure 100. Digital Processing Block Diagram
Offset Correction
ADS62P4X has an internal offset correction algorithm that estimates and corrects dc offset up to
±10 mV. The
correction can be enabled using the serial register bit ( OFFSET LOOP EN). Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using register bits (
OFFSET LOOP TC) as described in Table 22.
Table 22. Time Constant of Offset Correction Algorithm
<OFFSET LOOP TC>
TIME CONSTANT (TCCLK),
TIME CONSTANT, sec
D6-D5-D4
number of clock cycles
(= TCCLK × 1/Fs)
(1)
000
227
1.1
001
226
0.55
010
225
0.27
011
224
0.13
100
228
2.15
101
229
4.3
110
227
1.1
111
227
1.1
(1)
Sampling frequency, Fs = 125 MSPS
Copyright
2007–2012, Texas Instruments Incorporated
61
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