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参数资料
| 型号： | ADSP-21371BSWZ-2B |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32BIT 266MHZ 208-LQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI |
| 时钟速率： | 266MHz |
| 非易失内存： | ROM（512 kB） |
| 芯片上RAM： | 128kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-LQFP 裸露焊盘 |
| 供应商设备封装： | 208-LQFP-EP（28x28） |
| 包装： | 托盘 |
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ADSP-21371
Note the definitions of various clock periods shown in Table 12
which are a function of CLKIN and the appropriate ratio con
trol shown in Table 11.
Table 11. ADSP-21371 CLKOUT and CCLK Clock
Generation Operation
Timing
Requirements
CLKIN
CCLK
Description
Input Clock
Core Clock
Calculation
1/tCK
1/tCCLK
Table 12. Clock Periods
Timing
Requirements
Description1
tCK
CLKIN Clock Period
tCCLK
(Processor) Core Clock Period
tPCLK
(Peripheral) Clock Period = 2 × tCCLK
tSCLK
Serial Port Clock Period = (tPCLK) × SR
tSDCLK
SDRAM Clock Period = (tCCLK) × SDR
tSPICLK
SPI Clock Period = (tPCLLK) × SPIR
1 where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV
bits in DIVx register)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register
setting)
SDR=SDRAM-to-Core Clock Ratio (Values determined by bits 20-18 of the
PMCTL register)
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 36 on Page 44 under Test Conditions for voltage refer
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Rev. 0
|
Page 18 of 48
|
June 2007
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21371BSWZ-2B2 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor optimized for high performance audio processing |
| ADSP-21371KSWZ-2A | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit/40-Bit 266MHz 266MIPS 208-Pin LQFP EP 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT/40-BIT 266MHZ 266MIPS 208LQFP EP - Trays 制造商:Rochester Electronics LLC 功能描述: |
| ADSP-21371KSWZ-2A2 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor optimized for high performance audio processing |
| ADSP-21371KSWZ-2B | 功能描述:IC DSP 32BIT 266MHZ 208-LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21371KSWZ-2B2 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor optimized for high performance audio processing |
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