收藏本站
参数资料
型号： ADSP-21371BSWZ-2B
厂商： Analog Devices Inc
文件页数： 22/48页
文件大小： 0K
描述： IC DSP 32BIT 266MHZ 208-LQFP
产品培训模块： SHARC Processor Overview
标准包装： 1
系列： SHARC®
类型： 浮点
接口： DAI，DPI
时钟速率： 266MHz
非易失内存： ROM（512 kB）
芯片上RAM： 128kB
电压 - 输入/输出： 3.30V
电压 - 核心： 1.20V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 208-LQFP 裸露焊盘
供应商设备封装： 208-LQFP-EP（28x28）
包装： 托盘
ADSP-21371
Serial Ports
To determine whether communication is possible between two
Serial port signals (SCLK, FS, Data Channel A, Data Channel B)
devices at clock speed n, the following specifications must be
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
confirmed: 1) frame sync delay and frame sync setup and hold,
timing specifications provided below are valid at the
2) data delay and data setup and hold, and 3) SCLK width.
DAI_P20–1 pins.
Table 27. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
2.5
ns
tHFSE
1
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
2.5
ns
tSDRE
1
Receive Data Setup Before Receive SCLK
2.5
ns
tHDRE
1
Receive Data Hold After SCLK
2.5
ns
tSCLKW
SCLK Width
10
ns
tSCLK
SCLK Period
20
ns
Switching Characteristics
tDFSE
2
FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
10.5
ns
tHOFSE
2
FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode)
2
ns
tDDTE
2
Transmit Data Delay After Transmit SCLK
11
ns
tHDTE
2
Transmit Data Hold After Transmit SCLK
2
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 28. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
1
FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)
tHFSI
1
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
tSDRI
1
Receive Data Setup Before SCLK
tHDRI
1
Receive Data Hold After SCLK
Switching Characteristics
tDFSI
2
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
tHOFSI
2
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
tDFSIR
2
FS Delay After SCLK (Internally Generated FS in Receive Mode)
tHOFSIR
2
FS Hold After SCLK (Internally Generated FS in Receive Mode)
tDDTI
2
Transmit Data Delay After SCLK
tHDTI
2
Transmit Data Hold After SCLK
tSCKLIW
Transmit or Receive SCLK Width
7
2.5
7
2.5
–1.0
0.5tSCLK – 2
4
10.7
3.6
0.5tSCLK + 2
ns
1 Referenced to the sample edge.
2 Referenced to drive edge.
Rev. 0
|
Page 29 of 48
|
June 2007
相关PDF资料
PDF描述
ADSP-21469BBCZ-3 IC DSP 32/40BIT 400MHZ 324BGA
ADSP-21479BBCZ-2A IC DSP SHARC 266MHZ LP 196CSPBGA
ADSP-21479KBCZ-3A IC DSP SHARK 300MHZ 196CSPBGA
ADSP-21489BSWZ-3B IC CCD SIGNAL PROCESSOR 176LQFP
ADSP-2171BSTZ-133 IC DSP CONTROLLER 16BIT 128TQFP
相关代理商/技术参数
参数描述
ADSP-21371BSWZ-2B2 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor optimized for high performance audio processing
ADSP-21371KSWZ-2A 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit/40-Bit 266MHz 266MIPS 208-Pin LQFP EP 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT/40-BIT 266MHZ 266MIPS 208LQFP EP - Trays 制造商:Rochester Electronics LLC 功能描述:
ADSP-21371KSWZ-2A2 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor optimized for high performance audio processing
ADSP-21371KSWZ-2B 功能描述:IC DSP 32BIT 266MHZ 208-LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP-21371KSWZ-2B2 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor optimized for high performance audio processing
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*