- 您现在的位置：买卖IC网 > PDF目录1899 > ADSP-21469BBCZ-3 (Analog Devices Inc)IC DSP 32/40BIT 400MHZ 324BGA PDF资料下载
参数资料
| 型号： | ADSP-21469BBCZ-3 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/72页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32/40BIT 400MHZ 324BGA |
| 产品变化通告： | Pin Function Change 08/Mar/2012 |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SCI，SPI，SSP，UART/USART |
| 时钟速率： | 400MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 5Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.05V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 324-BGA，CSPBGA |
| 供应商设备封装： | 324-CSPBGA |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
ADSP-21469
Rev. 0
|
Page 21 of 72
|
June 2010
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 45 on Page 58 under Test Conditions for voltage refer-
ence levels.
In the following sections, Switching Characteristics specify how
the processor changes its signals. Circuitry external to the pro-
cessor must be designed for compatibility with these signal
characteristics. Switching characteristics describe what the pro-
cessor will do in a given circumstance. Use switching
characteristics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.
In the following sections, Timing Requirements apply to signals
that are controlled by circuitry external to the processor, such as
the data input for a read operation. Timing requirements guar-
antee that the processor operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 5). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
The product of CLKIN and PLLM must never exceed 1/2 of
(INDIV = 0).
The product of CLKIN and PLLM must never exceed
(INDIV = 1).
The VCO frequency is calculated as follows:
fVCO = 2 × PLLM × fINPUT
fCCLK = (2 × PLLM × fINPUT) ÷ (PLLD)
where:
fVCO = VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = Divider value 2, 4, 8, or 16 based on the PLLD value
programmed on the PMCTL register. During reset this value
is 2.
fINPUT = input frequency to the PLL
fINPUT = CLKIN when the input divider is disabled, or
fINPUT = CLKIN 2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in and
Table 16. All of the timing specifications for the ADSP-21469
peripherals are defined in relation to tPCLK. See the peripheral
specific section for each peripheral’s timing information.
Figure 5 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-214xx SHARC Processor Hard-
ware Reference.
Table 16. Clock Periods
Timing
Requirements
Description
tCK
CLKIN Clock Period
tCCLK
Processor Core Clock Period
tPCLK
Peripheral Clock Period = 2 × tCCLK
相关PDF资料 |
PDF描述 |
|---|---|
| ADSP-21479BBCZ-2A | IC DSP SHARC 266MHZ LP 196CSPBGA |
| ADSP-21479KBCZ-3A | IC DSP SHARK 300MHZ 196CSPBGA |
| ADSP-21489BSWZ-3B | IC CCD SIGNAL PROCESSOR 176LQFP |
| ADSP-2171BSTZ-133 | IC DSP CONTROLLER 16BIT 128TQFP |
| ADSP-2181KSZ-160 | IC DSP CONTROLLER 16BIT 128-PQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21469KBCZ-3 | 功能描述:IC DSP 32/40BIT 400MHZ 324BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21469KBCZ-4 | 功能描述:IC DSP 32/40BIT 450MHZ 324BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP21469KBCZENG | 制造商:Analog Devices 功能描述: |
| ADSP-21469KBCZ-ENG | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
| ADSP-21469KBCZ-X | 制造商:Analog Devices 功能描述:FXD PT PROC - Trays |
发布紧急采购，3分钟左右您将得到回复。