- 您现在的位置：买卖IC网 > PDF目录19399 > ADSP-21478KSWZ-1A (Analog Devices Inc)IC DSP SHARC 200MHZ LP 100LQFP PDF资料下载
参数资料
| 型号： | ADSP-21478KSWZ-1A |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/72页 |
| 文件大小： | 0K |
| 描述： | IC DSP SHARC 200MHZ LP 100LQFP |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 时钟速率： | 200MHz |
| 非易失内存： | ROM（4Mb） |
| 芯片上RAM： | 3Mb |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP 裸露焊盘 |
| 供应商设备封装： | 100-LQFP-EP（14x14） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
Rev. A
|
Page 24 of 72
|
September 2011
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 18. While no specific power-up sequencing is required
between VDD_EXT and VDD_INT, there are some considerations
that the system designs should take into account.
No power supply should be powered up for an extended
period of time (>200 ms) before another supply starts to
ramp up.
If the VDD_INT power supply comes up after VDD_EXT, any
pin, such as RESETOUT and RESET, may actually drive
momentarily until the VDD_INT rail has powered up. Systems
sharing these signals on the board must determine if there
are any issues that need to be addressed based on this
behavior.
Note that during power-up, when the VDD_INT power supply
comes up after VDD_EXT, a leakage current of the order of three-
state leakage current pull-up, pull-down, may be observed on
any pin, even if that is an input only (for example, the RESET
pin), until the VDD_INT rail has powered up.
Figure 5. Core Clock and System Clock Relationship to CLKIN
LOOP
FILTER
CLKIN
PCLK
SDRAM
DIVIDER
BYPASS
MUX
PMCTL
(SDCKR)
CCLK
PLL
XTAL
CLKIN
DIVIDER
RESET
f
VCO ÷ (2 × PLLM)
BUF
VCO
BUF
PMCTL
(INDIV)
PLL
DIVIDER
RESETOUT
CLKOUT (TEST ONLY)*
DELAY OF
4096 CLKIN
CYCLES
PCLK
PMCTL
(PLLBP)
PMCTL
(PLLD)
f
VCO
f
CCLK
fINPUT
*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f
INPUT.
THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.
CLK_CFGx/
PMCTL (2 × PLLM)
DIVIDE
BY 2
PIN
MUX
PMCTL
(PLLBP)
CCLK
RESETOUT
CORESRST
SDCLK
BYPASS
MUX
Table 18. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter
Min
Max
Unit
Timing Requirements
tRSTVDD
RESET Low Before VDD_EXT or VDD_INT On
0
ms
tIVDDEVDD
VDD_INT On Before VDD_EXT
–200
+200
ms
tCLKVDD
1
CLKIN Valid After VDD_INT and VDD_EXT Valid
0
200
ms
tCLKRST
CLKIN Valid Before RESET Deasserted
10
2
ms
tPLLRST
PLL Control Setup Before RESET Deasserted
20
3
ms
Switching Characteristic
tCORERST
Core Reset Deasserted After RESET Deasserted
4096 × tCK + 2 × tCCLK
4, 5
ms
1 Valid VDD_INT and VDD_EXT assumes that the supplies are fully ramped to their nominal values (it does not matter which supply comes up first). Voltage ramp rates can vary
from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem.
2 Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's data sheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3 Based on CLKIN cycles.
4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5 The 4096 cycle count depends on tSRST specification in Table 20. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
相关PDF资料 |
PDF描述 |
|---|---|
| ACM30DTMH | CONN EDGECARD 60POS R/A .156 SLD |
| VI-J6K-IZ | CONVERTER MOD DC/DC 40V 25W |
| ACM30DTMD | CONN EDGECARD 60POS R/A .156 SLD |
| TAJC335M050RNJ | CAP TANT 3.3UF 50V 20% 2312 |
| RW2-1209D/H2/SMD | CONV DC/DC 2W 9-18VIN +/-09VOUT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21478KSWZ-2A | 功能描述:IC DSP SHARC 266MHZ LP 100LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21478KSWZ-ENG | 制造商:Analog Devices 功能描述:SHARC PROCESSOR - Trays |
| ADSP-21479 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21479BBCZ-2A | 功能描述:IC DSP SHARC 266MHZ LP 196CSPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21479BBCZ-2AX | 制造商:Analog Devices 功能描述:- Trays |
发布紧急采购，3分钟左右您将得到回复。