参数资料
型号: ADSP-2188NKSTZ-320
厂商: Analog Devices Inc
文件页数: 32/48页
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 100LQFP
标准包装: 1
系列: ADSP-21xx
类型: 定点
接口: 主机接口,串行端口
时钟速率: 80MHz
非易失内存: 外部
芯片上RAM: 256kB
电压 - 输入/输出: 1.8V,2.5V,3.3V
电压 - 核心: 1.80V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
Rev. A
|
Page 38 of 48
|
August 2006
ADSP-218xN
IDMA Read, Short Read Cycle
Table 25. IDMA Read, Short Read Cycle
Parameter
1, 2
Min
Max
Unit
Timing Requirements:
tIKR
IACK Low Before Start of Read3
0ns
tIRP1
Duration of Read (DM/PM1)4
10
2tCK – 5
ns
tIRP2
Duration of Read (PM2)5
10
tCK – 5
ns
Switching Characteristics:
tIKHR
IACK High After Start of Read
10
ns
tIKDH
IAD15 – 0 Data Hold After End of Read
6
0ns
tIKDD
IAD15 – 0 Data Disabled After End of Read6
10
ns
tIRDE
IAD15 – 0 Previous Data Enabled After Start of Read
0
ns
tIRDV
IAD15 – 0 Previous Data Valid After Start of Read
10
ns
1 Short Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) Bit 14 of the IDMA overlay register, and is
disabled by default upon reset.
2 Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
3 Start of Read = IS Low and IRD Low.
4 DM Read or first half of PM Read.
5 Second half of PM Read.
6 End of Read = IS High or IRD High.
Figure 36. IDMA Read, Short Read Cycle
tIRP
tIKR
PREVIOUS
DATA
tIKHR
tIRDV
tIKDD
tIRDE
tIKDH
IAD15–0
IACK
IS
IRD
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