参数资料
型号: ADSP-BF532SBBZ400
厂商: Analog Devices Inc
文件页数: 53/64页
文件大小: 0K
描述: IC DSP CTLR 16BIT 400MHZ 169-BGA
产品培训模块: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
标准包装: 1
系列: Blackfin®
类型: 定点
接口: SPI,SSP,UART
时钟速率: 400MHz
非易失内存: ROM(1 kB)
芯片上RAM: 84kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 169-BBGA
供应商设备封装: 169-PBGA(19x19)
包装: 托盘
配用: ADZS-BF533-EZLITE-ND - KIT W/BOARD EVAL FOR ADSP-BF533
ADSP-BF531 / ADSP-BF532 / ADSP-BF533
169-BALL PBGA BALL ASSIGNMENT
Table 43 lists the PBGA ball assignment by signal. Table 44 on
Page 54 lists the PBGA ball assignment by ball number.
Table 43. 169-Ball PBGA Ball Assignment (Alphabetical by Signal)
Signal
ABE0
ABE1
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AWE
BG
BGH
BMODE0
BMODE1
BR
CLKIN
CLKOUT
DATA0
DATA1
DATA2
DATA3
Ball No.
H16
H17
J16
J17
K16
K17
L16
L17
M16
M17
N17
N16
P17
P16
R17
R16
T17
U15
T15
U16
T14
D17
E16
E17
F16
F17
C16
G16
G17
T13
U17
U5
T5
C17
A14
D16
U14
T12
U13
T11
Signal
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DR0PRI
DR0SEC
DR1PRI
DR1SEC
DT0PRI
DT0SEC
DT1PRI
DT1SEC
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Ball No.
U12
U11
T10
U10
T9
U9
T8
U8
U7
T7
U6
T6
M2
M1
H1
H2
K2
K1
F1
F2
U1
B16
F11
G7
G8
G9
G10
G11
H7
H8
H9
H10
H11
J7
J8
J9
J10
J11
K7
K8
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
MISO
MOSI
NMI
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PPI_CLK
PPI0
PPI1
PPI2
PPI3
RESET
RFS0
RFS1
RSCLK0
RSCLK1
RTCVDD
Ball No.
K9
K10
K11
L7
L8
L9
L10
L11
M9
T16
E2
E1
B11
D2
C1
B1
C2
A1
A2
B3
A3
B4
A4
B5
A5
A6
B6
A7
B7
B10
B9
A9
B8
A8
A12
N1
J1
N2
J2
F10
Signal
RTXI
RTXO
RX
SA10
SCAS
SCK
SCKE
SMS
SRAS
SWE
TCK
TDI
TDO
TFS0
TFS1
TMR0
TMR1
TMR2
TMS
TRST
TSCLK0
TSCLK1
TX
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V DDEXT
V DDEXT
V DDEXT
V DDEXT
V DDEXT
V DDEXT
V DDEXT
V DDEXT
Ball No.
A10
A11
T1
B15
A16
D1
B14
A17
A15
B17
U4
U3
T4
L1
G2
R1
P2
P1
T3
U2
L2
G1
R2
F12
G12
H12
J12
K12
L12
M10
M11
M12
B2
F6
F7
F8
F9
G6
H6
J6
Signal
V DDEXT
V DDEXT
V DDEXT
V DDEXT
V DDEXT
V DDEXT
VROUT0
VROUT1
XTAL
Ball No.
K6
L6
M6
M7
M8
T2
B12
B13
A13
Rev. I
|
Page 53 of 64 |
August 2013
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