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| 型号： | ADSP-BF537BBCZ-5B |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/68页 |
| 文件大小： | 0K |
| 描述： | IC DSP CTLR 16BIT 208CSPBGA |
| 产品培训模块： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | CAN，SPI，SSP，TWI，UART |
| 时钟速率： | 500MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 132kB |
| 电压 - 输入/输出： | 2.50V，3.30V |
| 电压 - 核心： | 1.26V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-LFBGA，CSPBGA |
| 供应商设备封装： | 208-CSPBGA |
| 包装： | 托盘 |
| 配用： | ADZS-BF537-ASKIT-ND - BOARD EVAL SKIT ADSP-BF537 ADZS-BFAUDIO-EZEXT-ND - BOARD EVAL AUDIO BLACKFIN ADZS-BF537-EZLITE-ND - BOARD EVAL ADSP-BF537 ADZS-BFAV-EZEXT-ND - BOARD DAUGHT ADSP-BF533,37,61KIT ADZS-BF537-STAMP-ND - SYSTEM DEV FOR ADSP-BF537 |
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Rev. J
|
Page 13 of 68
|
February 2014
Output Mode
Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hard-
ware signaling.
ITU-R 656 Mode Descriptions
The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applica-
tions. Three distinct submodes are supported:
1. Active video only mode
2. Vertical blanking only mode
3. Entire field mode
Active Video Mode
Active video only mode is used when only the active video por-
tion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_COUNT register).
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
DYNAMIC POWER MANAGEMENT
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
vide five operating modes, each with a different performance
and power profile. In addition, dynamic power management
provides the control functions to dynamically alter the proces-
sor core supply voltage, further reducing power dissipation.
Control of clocking to each of the peripherals also reduces
power consumption. See Table 4 for a summary of the power
settings for each mode. Also, see Table 16, Table 15 and
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power
Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured
L1 memories.
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting wake-up causes the processor
to sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the
processor to transition to the active mode. Assertion of RESET
while in deep sleep mode causes the processor to transition to
the full-on mode.
Table 4. Power Settings
Mode
PLL
Bypassed
Core
Clock
(CCLK)
System
Clock
(SCLK)
Internal
Power
(VDDINT)
Full On
Enabled
No
Enabled
On
Active
Enabled/
Disabled
Yes
Enabled
On
Sleep
Enabled
—
Disabled Enabled
On
Deep
Sleep
Disabled
—
Disabled Disabled On
Hibernate Disabled
—
Disabled Disabled Off
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-BF537BBCZ-5BV | 功能描述:IC DSP CTLR 16BIT 208CSPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF537BBCZ5BVX | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF537BBCZ-5BX | 制造商:Analog Devices 功能描述:208-MEG PB FREE SPARSE - Trays |
| ADSP-BF537KBC-6A | 制造商:Analog Devices 功能描述:DSP FIX PT 16BIT 600MHZ 600MIPS 182CSPBGA - Trays |
| ADSP-BF537KBCZ-6A | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 600MHz 600MIPS 182-Pin CSP-BGA 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
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