参数资料
型号: ADSP-TS101SKB2250X
厂商: ANALOG DEVICES INC
元件分类: 数字信号处理
英文描述: 64-BIT, 125 MHz, OTHER DSP, PBGA484
封装: 19 X 19 MM, METRIC, PLASTIC, BGA-484
文件页数: 17/42页
文件大小: 774K
代理商: ADSP-TS101SKB2250X
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
24
REV. PrE
PRELIMINARY TECHNICAL DATA
DS2–0
Static pins – must be constant
———————
LCLKRAT2–0
Static pins – must be constant
———————
SCLKFREQ
Static pins – must be constant
———————
1 The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus
contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual.
2
CPA and DPA pins are open drains and have 0.5 k
internal pullups.
3 This pin is a strap option. During reset, an internal resistor pulls the pin low.
4 These pins have an asynchronous minimum pulse width of tSCLK + TBD ns.
5 These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. These synchronous specifications only apply for
recognition in the current clock reference cycle.
6 For additional requirement details, see Reset and Booting on page 9.
7 Reference clock depends on function.
8 These pins may change only during reset; recommend connecting it to VDD/VSS.
Figure 10. General AC parameters timing
Table 17. AC Signal Specifications (all values in this table are in nanoseconds) (continued)
Name
Description
Input
Setup
(min)
Input
H
o
ld
(m
in)
O
u
tput
V
a
lid
(max
)
O
u
tput
H
o
ld
(m
in)
O
u
tput
Enab
le
(m
ax)
1
O
u
tput
D
is
a
b
le
(max
)
1
R
e
fe
rence
C
lock
REFERENCE
CLOCK
INPUT
SIGNAL
OUTPUT
SIGNAL
THREE-
STATE
OUTPUT
VALID
OUTPUT
HOLD
OUTPUT
ENABLE
OUTPUT
DISABLE
INPUT
HOLD
INPUT
SETUP
1.5V
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