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| 型号： | ADSP-TS101SKB2250X |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封装： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件页数： | 9/42页 |
| 文件大小： | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
17
REV. PrE
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
PRELIMINARY TECHNICAL DATA
Table 8. Pin Definitions—Flags, Interrupts, and Timer
Signal
Type
Description
FLAG3–0
1
I/O/A
(pd)
FLAG pins. Bidirectional input/output pins can be used as program conditions. Each
pin can be configured individually for input or for output. FLAG3–0 are inputs after
power-up and reset.
IRQ3–02
I/A (pu)
Interrupt Request. When asserted, the DSP generates an interrupt. Each of the
IRQ3–0
pins can be independently set for edge-triggered or level-sensitive operation. After reset,
these pins are disabled unless the
IRQ3–0 strap option and interrupt vectors are
initialized for booting.
TMR0E1
O (pd)
Timer 0 expires. This output pulses for four SCLK cycles whenever timer 0 expires.
At reset this is a strap pin. For more information, see Table 14 on page 19.
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pulldown 100 k
; pu = internal pullup 100 k; T = Three-State
1 The internal 100 k
internal pulldown may not be sufficient depending on system noise and/or leakage. A stronger pulldown may be necessary.
2 The internal 100 k
internal pullup may not be sufficient depending on system noise and/or leakage. A stronger pullup may be necessary.
Table 9. Pin Definitions—Link Ports
Signal
Type
Description
L0DAT7–0
1
I/O
Link0 Data 7–0
L1DAT7–0
I/O
Link1 Data 7–0
L2DAT7–0
I/O
Link2 Data 7–0
L3DAT7–0
I/O
Link3 Data 7–0
L0CLKOUT
O
Link0 Clock/Acknowledge Output
L1CLKOUT
O
Link1 Clock/Acknowledge Output
L2CLKOUT
O
Link2 Clock/Acknowledge Output
L3CLKOUT
O
Link3 Clock/Acknowledge Output
L0CLKIN
I/A
Link0 Clock/Acknowledge Input
L1CLKIN
I/A
Link1 Clock/Acknowledge Input
L2CLKIN
I/A
Link2 Clock/Acknowledge Input
L3CLKIN
I/A
Link3 Clock/Acknowledge Input
L0DIR
O
Link0 Direction. (0 = input, 1 = output)
L1DIR
O
Link1 Direction. (0 = input, 1 = output)
L2DIR
2
O (pd)
Link2 Direction. (0 = input, 1 = output)
At reset this is a strap pin. For more information, see Table 14 on page 19.
L3DIR
O (pd)
Link3 Direction. (0 = input, 1 = output)
A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pulldown 100 k
; pu = internal pullup 100 k; T = Three-State
1 The link port data pins, if connected or floated for extended periods (i.e., token slave with no token master), do not require pullups or pulldowns as there
are no reliability issues and the worst-case power consumption for these floating inputs is negligible. Floating in this case means that these inputs are not
driven by any source and that DC-biased terminations are not present.
2 The internal 100 k
internal pulldown may not be sufficient depending on system noise and/or leakage. A stronger pulldown may be necessary.
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| ADSP-TS201SABP-050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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| ADSP-TS201SABP-10X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-15X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-ENG | 制造商:Analog Devices 功能描述: |
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