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参数资料
| 型号： | ADSP-TS101SKB2250X |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 64-BIT, 125 MHz, OTHER DSP, PBGA484 |
| 封装： | 19 X 19 MM, METRIC, PLASTIC, BGA-484 |
| 文件页数： | 40/42页 |
| 文件大小： | 774K |
| 代理商： | ADSP-TS101SKB2250X |
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This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
7
REV. PrE
For current information contact Analog Devices at 800/262-5643
ADSP-TS101S
February 2002
PRELIMINARY TECHNICAL DATA
SDRAM Controller
The SDRAM controller controls the ADSP-TS101S’s transfers
of data to and from synchronous DRAM (SDRAM) at a through-
put of 32 or 64 bits per SCLK cycle using the external port and
SDRAM control pins.
The SDRAM interface provides a glueless interface with
standard SDRAMs—16M bit, 64M bit, 128M bit, and
256M bit. The DSP supports directly a maximum of
64M words
× 32 bit of SDRAM. The SDRAM interface is
mapped in external memory in the DSP’s unified memory map.
EPROM Interface
The ADSP-TS101S can be configured to boot from external 8-
bit EPROM at reset through the external port. An automatic
process (which follows reset) loads a program from the EPROM
into internal memory. This process uses sixteen wait cycles for
each read access. During booting, the
BMS pin functions as the
EPROM chip select signal. The EPROM boot procedure uses
DMA channel 0, which packs the bytes into 32-bit instructions.
Applications can also access the EPROM (write flash memories)
during normal operation through DMA.
The EPROM or Flash Memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16M bytes (twenty-four address bits). The
EPROM or Flash Memory interface can be used after boot via a
DMA.
Figure 3. ADSP-TS101S Shared Memory Multiprocessing System
CLKS/REFS
ADDR31–0
DATA63–0
BR1
BR7–2,0
ADDR31–0
DATA63–0
BR0
BR7–1
BMS
CONTROL
ADSP-TS101 #0
CONTROL
ADSP-TS101 #1
ADSP-TS101 #7
ADSP-TS101 #6
ADSP-TS101 #5
ADSP-TS101 #4
ADSP-TS101 #3
ADSP-TS101 #2
RESET
ID2–0
CLKS/REFS
LCLK_P
S/LCLK_N
VREF
SCLK_P
LCLKRAT2–0
SCLKFREQ
000
CLOCK
REFERENCE
VOLTAGE
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
OE
ADDR
DATA
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
RD
MS1–0
ACK
ID2–0
001
HBG
HBR
CS
WE
WRH/L
C
O
N
T
R
O
L
A
D
R
E
S
D
A
T
A
C
O
N
T
R
O
L
A
D
R
E
S
D
A
T
A
SDRAM
MEMORY
(OPTIONAL)
MSSD
FLYBY
IOEN
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
CLK
MSH
DMAR3–0
DPA
BOFF
CPA
BRST
LINK
DEVICES
(4 MAX)
(OPTIONAL)
LXCLKIN
LXDIR
LXDAT7–0
LXCLKOUT
TMR0E
BM
CONTROLIMP2–0
LINK
IRQ3–0
FLAG3–0
LINK
RESET
BUSLOCK
CLOCK
DS2–0
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相关代理商/技术参数 |
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| ADSP-TS201SABP-050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-TS201SABP-060 | 功能描述:IC PROCESSOR 600MHZ 576BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:TigerSHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-TS201SABP-10X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-15X | 制造商:Analog Devices 功能描述: |
| ADSP-TS201SABP-ENG | 制造商:Analog Devices 功能描述: |
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