参数资料
| 型号： | ADT7467BBZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADT7467 |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 1 |
| 系列： | dBCool® |
| 传感器类型： | 温度 |
| 传感范围： | -40°C ~ 120°C |
| 接口： | SMBus（2 线/I²C） |
| 灵敏度： | ±1.5°C |
| 电源电压： | 3 V ~ 5.5 V |
| 嵌入式： | 否 |
| 已供物品： | 板，缆线，CD |
| 已用 IC / 零件： | ADT7467 |
| 其它名称： | EVAL-ADT7467EBZ EVAL-ADT7467EBZ-ND |
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ADT7467
Write Operations
The SMBus specification defines several protocols for
different types of read and write operations. The ones used
in the ADT7467 are discussed here. The following
8. The master asserts a stop condition on SDA to end
the transaction.
This operation is illustrated in Figure 19.
abbreviations are used in Figure 18 through Figure 20:
1
2
3
4
5
6
7 8
S = start
P = stop
S
Slave
Address
W A
Slave
Address
A Data A P
R = read
W = write
A = acknowledge
A = no acknowledge
The ADT7467 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single
command byte to a slave device as follows:
1. The master device asserts a start condition on
SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts an
acknowledge on SDA.
4. The master sends a command code.
5. The slave asserts an acknowledge on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
For the ADT7467, the send byte protocol is used to write
a register address to RAM for a subsequent single byte read
from the same address. This operation is illustrated in
Figure 18.
Figure 19. Single Byte Write to a Register
Read Operations
The ADT7467 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address must have been set up
previously. In this operation, the master device receives a
single byte from a slave device as follows:
1. The master device asserts a start condition on
SDA.
2. The master sends the 7-bit slave address followed
by the read bit (high).
3. The addressed slave device asserts an
acknowledge on SDA.
4. The master receives a data byte.
5. The master asserts a no acknowledge on SDA.
6. The master asserts a stop condition on SDA, and
the transaction ends.
In the ADT7467, the receive byte protocol is used to read
a single byte of data from a register whose address has
previously been set by a send byte or write byte operation.
1
2
3
4
5 6
This operation is illustrated in Figure 20.
S
A
A P
Address W
Slave Register
Address
Figure 18. Setting a Register Address for
1
S
2
Slave
Address
3
R A
4
Data
5 6
A P
Subsequent Read
If the master is required to read data from the register
directly after setting up the address, it can assert a repeat start
condition immediately after the final acknowledge and carry
out a single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte
and one data byte to the slave device as follows:
1. The master device asserts a start condition on
SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts an
acknowledge on SDA.
4. The master sends a command code.
5. The slave asserts an acknowledge on SDA.
6. The master sends a data byte.
7. The slave asserts an acknowledge on SDA.
Figure 20. Single Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus
devices that allows an interrupting device to identify itself
to the host when multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the
following procedure occurs:
1. SMBALERT is pulled low.
2. The master initiates a read operation and sends the
alert response address (ARA = 0001 100). This is
a general call address that must not be used as a
specific device address.
3. The device whose SMBALERT output is low
responds to the alert response address, and the
master reads its device address. The address of the
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