参数资料
型号: ADT7467BBZEVB
厂商: ON Semiconductor
文件页数: 19/72页
文件大小: 0K
描述: BOARD EVALUATION FOR ADT7467
产品变化通告: MFG CHG Notification ADI to ON Semi
标准包装: 1
系列: dBCool®
传感器类型: 温度
传感范围: -40°C ~ 120°C
接口: SMBus(2 线/I²C)
灵敏度: ±1.5°C
电源电压: 3 V ~ 5.5 V
嵌入式:
已供物品: 板,缆线,CD
已用 IC / 零件: ADT7467
其它名称: EVAL-ADT7467EBZ
EVAL-ADT7467EBZ-ND
ADT7467
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to
the start bit (Bit 0) of Configuration Register 1 (0x40). By
default, the ADT7463 powers up with this bit set. The ADC
measures each analog input in turn and, as each
measurement is completed, the result is automatically stored
in the appropriate value register. This round-robin
monitoring cycle continues unless disabled by writing a 0 to
Bit 0 of Configuration Register 1.
As the ADC is normally left to free-run in this manner, the
a status bit is set, indicating an out-of-limit condition, it
remains set until read, even if the event that caused it is
absent. The only way to clear the status bit is to read the
status register after the event is absent. Interrupt mask
registers (0x74 and 0x75) allow masking of individual
interrupt sources to prevent an SMBALERT. However, if a
masked interrupt source goes out of limit, its associated
status bit is set in the interrupt status registers.
Table 19. STATUS REGISTER 1 (REG. 0X41)
time to monitor all analog inputs is normally not of interest
because the most recently measured value of an input can be
read at any time.
For applications where the monitoring cycle time is
important, it can be calculated easily. The total number of
channels measured is
? One Dedicated Supply Voltage Input (V CCP )
? One Supply Voltage (V CC Pin)
? One Local Temperature
? Two Remote Temperatures
As mentioned previously, the ADC performs round-robin
conversions. The total monitoring cycle time for averaged
voltage and temperature monitoring is 145 ms. The total
Bit
7
6
5
4
2
1
Mnemonic
OOL
R2T
LT
R1T
V CC
V CCP
Description
1 denotes a bit in Status Register 2 is set
and Status Register 2 should be read.
1 indicates that the Remote 2
temperature high or low limit has been
exceeded.
1 indicates that the Local temperature
high or low limit has been exceeded.
1 indicates that the Remote 1
temperature high or low limit has been
exceeded.
1 indicates that the V CC high or low limit
has been exceeded.
1 indicates that the V CCP high or low
limit has been exceeded.
monitoring cycle time for voltage and temperature
monitoring with averaging disabled is 19 ms. The ADT7467
Table 20. STATUS REGISTER 2 (REG. 0X42)
is a derivative of the ADT7468. As a result, the total
conversion time for the ADT7467 and ADT7468 are the
same, even though the ADT7467 has less monitored
channels.
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
Status Registers
The results of limit comparisons are stored in Interrupt
Status Register 1 and Interrupt Status Register 2. The status
register bit for each channel reflects the status of the last
measurement and limit comparison on that channel. If a
measurement is within limits, the corresponding status
register bit is cleared to 0. If the measurement is out of limit,
the corresponding status register bit is set to 1.
The state of the various measurement channels can be
polled by reading the status registers over the serial bus. In
Bit 7 (OOL) of Interrupt Status Register 1 (0x41), 1 means
that an out-of-limit event has been flagged in Interrupt
Bit
7
6
5
4
3
2
1
Mnemonic
D2
D1
F4P
FAN3
FAN2
FAN1
OVT
Description
1 indicates an open or short on
D2+/D2 ? inputs.
1 indicates an open or short on
D2+/D2 ? inputs.
1 indicates that Fan 4 has dropped
below minimum speed. Alternatively,
indicates that THERM timer limit has
been exceeded if the THERM timer
function is used.
1 indicates that Fan 3 has dropped
below minimum speed.
1 indicates that Fan 2 has dropped
below minimum speed.
1 indicates that Fan 1 has dropped
below minimum speed.
1 indicates that a THERM
overtemperature limit has been
exceeded.
Status Register 2. This means that the user also should read
Interrupt Status Register 2. Alternatively, Pin 5 or Pin 9 can
be configured as an SMBALERT output. This hardware
interrupt automatically notifies the system supervisor of an
out-of-limit condition. Reading the status registers clears the
appropriate status bit if the error condition that caused the
interrupt is absent. Status register bits are sticky. Whenever
Interrupts
SMBALERT Interrupt Behavior
The ADT7467 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status
bits behave when writing interrupt handler software.
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