参数资料
| 型号： | ADT7467BBZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 22/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADT7467 |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 1 |
| 系列： | dBCool® |
| 传感器类型： | 温度 |
| 传感范围： | -40°C ~ 120°C |
| 接口： | SMBus（2 线/I²C） |
| 灵敏度： | ±1.5°C |
| 电源电压： | 3 V ~ 5.5 V |
| 嵌入式： | 否 |
| 已供物品： | 板，缆线，CD |
| 已用 IC / 零件： | ADT7467 |
| 其它名称： | EVAL-ADT7467EBZ EVAL-ADT7467EBZ-ND |
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ADT7467
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7467 can generate SMBALERTs when a
programmable THERM timer limit has been exceeded. This
allows the system designer to ignore brief, infrequent
THERM assertions while capturing longer THERM timer
events. Register 0x7A is the THERM timer limit register.
This 8-bit register allows a limit from 0 sec (first THERM
assertion) to 5.825 sec to be set before an SMBALERT is
generated. The THER M timer value is compared with the
contents of the THERM timer limit register. If the THERM
timer value exceeds the THERM timer limit, the F4P bit
(Bit 5) of Interrupt Status Register 2 is set and an
2.914 s
1.457 s
SMBALERT is generated. Note that the F4P bit (Bit 5) of
Interrupt Mask Register 2 (0x75) masks SMBALERT if this
bit is set to 1; however, the F4P bit of Interrupt Status
Register 2 remains set if the THERM timer limit is
exceeded.
Figure 31 is a functional block diagram of the THERM
timer, limit, and associated circuitry. Writing a value of 0x00
to the THERM timer limit register (0x7A) causes
SMBALERT to be generated upon the first THERM
assertion. A THERM timer limit value of 0x01 generates an
SMBALERT once cumulative THERM assertions exceed
45.52 ms.
2.914 s
1.457 s
THERM LIMIT
(REG. 0x7A)
728.32 ms
364.16 ms
182.08 ms
91.04 ms
45.52 ms
22.76 ms
0 1 2 3 4 5 6 7
7 6 5 4 3 2 1 0
728.32 ms
364.16 ms
182.08 ms
91.04 ms
45.52 ms
22.76 ms
THERM TIMER
(REG. 0x79)
THERM
THERM TIMER CLEARED ON READ
COMPARATOR
IN OUT
LATCH
RESET
CLEARED
ON READ
F4P BIT (BIT 5)
STATUS REGISTER 2
1 = MASK
F4P BIT (BIT 5)
SMBALERT
MASK REGISTER 2
(REG. 0x75)
Figure 31. Functional Diagram of THERM Monitoring Circuitry
Configuring THERM Behavior
1. Configure the relevant pin as the THERM timer
input:
Setting Bit 1 (THERM timer enable) of
Configuration Register 3 (0x78) enables the
THERM timer monitoring functionality. This is
disabled on Pin 9 by default.
Setting Bit 0 and Bit 1 (Pin 9 Func) of
Configuration Register 4 (0x7D) enables THERM
timer/output functionality on Pin 9 (Bit 1,
THERM, of Configuration Register 3 must also be
set). Pin 9 can also be used as TACH4.
2. Select the desired fan behavior for THERM timer
events:
Assuming that the fans are running, setting Bit 2
(BOOST bit) of Configuration Register 3 (0x78)
causes all fans to run at 100% duty cycle whenever
THERM is asserted. This allows fail-safe system
cooling. If this bit is 0, the fans run at their current
settings and are not affected by THERM events. If
the fans are not already running when THERM is
asserted, the fans do not run to full speed.
3. Select whether THERM timer events should
generate SMBALERT interrupts:
When set, Bit 5 (F4P) of Mask Register 2 (0x75)
masks SMBALERTs when the THERM timer limit
value is exceeded. This bit should be cleared if
SMBALERT based on THERM events are
required.
4. Select a suitable THERM limit value:
This value determines whether an SMBALERT is
generated upon the first THERM assertion, or if
only a cumulative THERM assertion time limit is
exceeded. A value of 0x00 causes an SMBALERT
to be generated upon the first THERM assertion.
5. Select a THERM monitoring time:
This value specifies how often OS or BIOS level
software checks the THERM timer. For example,
http://onsemi.com
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