参数资料
型号: ADT7475EBZEVB
厂商: ON Semiconductor
文件页数: 18/58页
文件大小: 0K
描述: BOARD EVALUATION FOR ADT7475
产品变化通告: MFG CHG Notification ADI to ON Semi
标准包装: 1
系列: dBCool®
类型: 温度传感器
适用于相关产品: ADT7475
所含物品: 评估板
其它名称: EVAL-ADT7475EB
EVAL-ADT7475EB-ND
ADT7475
Table 24. INTERRUPT STATUS REGISTER 1
(REG. 0X41)
Bit Mnemonic Description
7 OOL 1 denotes that a bit in Status Register 2
is set and that Interrupt Status
Register 2 should be read.
6 R2T 1 indicates that the Remote 2
Temperature High or Low Limit has
been exceeded.
Figure 24 shows how the SMBALERT output and sticky
status bits behave. Once a limit is exceeded, the
corresponding status bit is set to 1. The status bit remains set
until the error condition subsides and the status register is
read. The status bits are referred to as sticky because they
remain set until read by software. This ensures that an
out-of-limit event cannot be missed if software is polling the
device periodically. Note that the SMBALERT output
remains low for the entire duration that a reading is
5
4
2
1
LT
R1T
V CC
V CCP
1 indicates that the Local Temperature
High or Low Limit has been exceeded.
1 indicates that the Remote 1
Temperature High or Low Limit has
been exceeded.
1 indicates that the V CC High or Low
Limit has been exceeded.
1 indicates that the V CCP High or Low
Limit has been exceeded.
out-of-limit and until the interrupt status register has been
read. This has implications for how software handles the
interrupt.
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing
interrupts, it is recommended to handle the SMBALERT
interrupt as follows:
1. Detect the SMBALERT assertion.
Table 25. INTERRUPT STATUS REGISTER 2
(REG. 0X42)
Bit Mnemonic Description
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
source.
4. Mask the interrupt source by setting the
7
6
5
4
3
D2
D1
F4P
FAN3
FAN2
1 indicates an open or short on
D2+/D2 ? inputs.
1 indicates an open or short on
D1+/D1 ? inputs.
1 indicates that Fan 4 has dropped
below minimum speed. Alternatively,
indicates that THERM timer limit has
been exceeded, if the THERM function
is used.
1 indicates that Fan 3 has dropped
below minimum speed.
1 indicates that Fan 2 has dropped
below minimum speed.
appropriate mask bit in the interrupt mask registers
(0x74 and 0x75).
5. Take the appropriate action for a given interrupt
source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the
interrupt status bit has cleared, reset the
corresponding interrupt mask bit to 0. This causes
the SMBALERT output and status bits to behave
as shown in Figure 25.
HIGH LIMIT
2
1
FAN1
OVT
1 indicates that Fan 1 has dropped
below minimum speed.
1 indicates that a THERM
overtemperature limit has been
exceeded.
TEMPERATURE
CLEARED ON READ
“STICKY”
(TEMP BELOW LIMIT)
SMBALERT Interrupt Behavior
The ADT7475 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. Note
STATUS BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
how the SMBALERT output and status bits behave when
writing interrupt handler software.
SMBALERT
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
HIGH LIMIT
TEMPERATURE
CLEARED
(SMBALERT RE-ARMED)
Figure 25. How Masking the Interrupt Source Affects
SMBALERT Output
“STICKY”
STATUS BIT
SMBALERT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
CLEARED ON READ
(TEMP BELOW LIMIT)
Masking Interrupt Sources
Interrupt Mask Register 1 (0x74) and Interrupt Mask
Register 2 (0x75) allow individual interrupt sources to be
masked out to prevent SMBALERT interrupts. Note that
masking an interrupt source prevents only the SMBALERT
Figure 24. SMBALERT and Status Bit Behavior
output from being asserted; the appropriate status bit is set
normally.
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