参数资料
| 型号： | ADT7475EBZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 48/58页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADT7475 |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 1 |
| 系列： | dBCool® |
| 类型： | 温度传感器 |
| 适用于相关产品： | ADT7475 |
| 所含物品： | 评估板 |
| 其它名称： | EVAL-ADT7475EB EVAL-ADT7475EB-ND |
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ADT7475
Table 58. FAN TACHOMETER LIMIT REGISTERS (Note 1)
Register Address
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
TACH1 Minimum Low Byte
TACH1 Minimum High Byte/Single-channel ADC Channel Select
TACH2 Minimum Low Byte
TACH2 Minimum High Byte
TACH3 Minimum Low Byte
TACH3 Minimum High Byte
TACH4 Minimum Low Byte
TACH4 Minimum High Byte
Power-On Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
1. Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set
in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 Lock bit has no effect on these registers.
Table 59. REGISTER 0X55 ? TACH1 MINIMUM HIGH BYTE (POWER-ON DEFAULT = 0XFF)
Bit No.
<4:0>
<7:5>
Mnemonic
Reserved
SCADC
R/W
Read-only
R/W
Description
These bits are reserved when Bit 6 of Configuration Register 2 (0x73) is set (single-channel ADC
mode). Otherwise, these bits represent Bits <4:0> of the TACH1 minimum high byte register.
When Bit 6 of Configuration Register 2 (0x73) is set (single-channel ADC mode), these bits are
used to select the only channel from which the ADC makes measurements. Otherwise, these
bits represent Bits <7:5> of the TACH1 minimum high byte register.
Table 60. PWM CONFIGURATION REGISTERS (Note 1)
Register Address
0x5C
0x5D
0x5E
R/W
R/W
R/W
R/W
PWM1 Configuration
PWM2 Configuration
PWM3 Configuration
Description
Power-On Default
0x62
0x62
0x62
1. These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 61. REGISTER 0X05C, REGISTER 0X5D, AND REGISTER 0X5E ? PWM CONFIGURATION REGISTERS
(POWER-ON DEFAULT = 0X62)
Bit No.
<2:0>
<4>
<7:5>
Mnemonic
SPIN
INV
BHVR
R/W
R/W
R/W
R/W
Description
These bits control the startup timeout for PWMx. The PWM output stays high until two valid
TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan
TACH measurement directly after the fan startup timeout period, the TACH measurement reads
0xFFFF and Interrupt Status Register 2 reflects the fan fault. If the TACH minimum high and low
bytes contain 0xFFFF or 0x0000, the Interrupt Status Register 2 bit is not set, even if the fan
has not started.
000 = No Startup Timeout
001 = 100 ms
010 = 250 ms (Default)
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for
100% duty cycle. Setting this bit to 1 inverts the PWM output so that 100% duty cycle
corresponds to a logic low output.
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 temperature controls PWMx (automatic fan control mode).
001 = Local temperature controls PWMx (automatic fan control mode).
010 = Remote 2 temperature controls PWMx (automatic fan control mode).
011 = PWMx runs full speed.
100 = PWMx disabled (default).
101 = Fastest speed calculated by local and Remote 2 temperature controls PWMx.
110 = Fastest speed calculated by all three temperature channel controls PWMx.
111 = Manual Mode. PWM duty cycle registers (0x30 to 0x32) become writable.
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