参数资料
| 型号： | ADT7475EBZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 54/58页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADT7475 |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 1 |
| 系列： | dBCool® |
| 类型： | 温度传感器 |
| 适用于相关产品： | ADT7475 |
| 所含物品： | 评估板 |
| 其它名称： | EVAL-ADT7475EB EVAL-ADT7475EB-ND |
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ADT7475
Table 75. REGISTER 0X73 ? CONFIGURATION REGISTER 2 (POWER-ON DEFAULT = 0X00) (Note 1)
Bit No.
<0:3>
<4>
<5>
<6>
Mnemonic
RES
AVG
ATTN
CONV
R/W
R/W
R/W
R/W
Description
Reserved.
AVG = 1, averaging on the temperature and voltage measurements is turned off. This allows
measurements on each channel to be made much faster.
ATTN = 1, the ADT7475 removes the attenuators from the V CCP input. The V CCP input can be
used for other functions such as connecting up external sensors.
CONV = 1, the ADT7475 is put into a single-channel ADC conversion mode. In this mode, the
ADT7475 can be made to read continuously from one input only, for example, Remote 1
temperature. The appropriate ADC channel is selected by writing to Bits <7:5> of TACH1
minimum high byte register (0x55).
Register 0x55, Bits <7:5>
000 Reserved
001 V CCP
010 V CC (3.3 V)
011 Reserved
100 Reserved
101 Remote 1 Temperature
110 Local Temperature
111 Remote 2 Temperature
<7>
SHDN
R/W
SHDN = 1, ADT7475 goes into shutdown mode. All PWM outputs assert low (or high depending
on state of the INV bit) to switch off all fans. The PWM current duty cycle registers read 0x00 to
indicate that the fans are not being driven.
1. These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 76. REGISTER 0X74 ? INTERRUPT MASK REGISTER 1 (POWER-ON DEFAULT <7:0> = 0X00)
Bit No.
<1>
<2>
<4>
<5>
<6>
<7>
Mnemonic
V CCP
V CC
R1T
LT
R2T
OOL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
V CCP = 1, masks SMBALERT for out-of-limit conditions on the V CCP channel.
V CC = 1, masks SMBALERT for out-of-limit conditions on the V CC channel.
R1T = 1, masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.
LT = 1, masks SMBALERT for out-of-limit conditions on the local temperature channel.
R2T = 1, masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.
OOL = 0, when one or more alerts are generated in Interrupt Status Register 2, assuming that
all the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT is still asserted.
OOL = 1, when one or more alerts are generated in Interrupt Status Register 2, assuming that
all the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT is not asserted.
Table 77. REGISTER 0X75 ? INTERRUPT MASK REGISTER 2 (POWER-ON DEFAULT <7:0> = 0X00)
Bit No.
<1>
<2>
<3>
<4>
<5>
<6>
<7>
Mnemonic
OVT
FAN1
FAN2
FAN3
F4P
D1
D2
R/W
Read-only
R/W
R/W
R/W
R/W
R/W
R/W
Description
OVT = 1, masks SMBALERT for overtemperature THERM conditions.
FAN1 = 1, masks SMBALERT for a Fan 1 fault.
FAN2 = 1, masks SMBALERT for a Fan 2 fault.
FAN3 = 1, masks SMBALERT for a Fan 3 fault.
F4P = 1, masks SMBALERT for a Fan 4 fault. If the TACH4 pin is being used as the THERM
input, this bit masks SMBALERT for a THERM timer event.
D1 = 1, masks SMBALERT for a diode open or short on a Remote 1 channel.
D2 = 1, masks SMBALERT for a diode open or short on a Remote 2 channel.
Table 78. REGISTER 0X76 ? EXTENDED RESOLUTION REGISTER 1 (Note 1)
Bit No.
<3:2>
<5:4>
Mnemonic
V CCP
V CC
R/W
R/W
R/W
Description
V CCP LSBs. Holds the 2 LSBs of the 10-bit V CCP measurement.
V CC LSBs. Holds the 2 LSBs of the 10-bit V CC measurement.
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
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