参数资料
型号: ADT7475EBZEVB
厂商: ON Semiconductor
文件页数: 27/58页
文件大小: 0K
描述: BOARD EVALUATION FOR ADT7475
产品变化通告: MFG CHG Notification ADI to ON Semi
标准包装: 1
系列: dBCool®
类型: 温度传感器
适用于相关产品: ADT7475
所含物品: 评估板
其它名称: EVAL-ADT7475EB
EVAL-ADT7475EB-ND
ADT7475
speed control mode or acoustic enhancement mode. See the
Programming the Automatic Fan Speed Control Loop
section for details.
Operating from 3.3 V Standby
The ADT7475 has been specifically designed to operate
from a 3.3 V STBY supply. In computers that support S3 and
S5 states, the core voltage of the processor is lowered in
these states. When monitoring THERM, the THERM timer
should be disabled during these states.
Standby Mode
The ADT7475 has been specifically designed to respond to
the STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor is lowered in these states.
When monitoring THERM, the THERM timer should be
disabled during these states.
When the V CCP voltage drops below the V CCP low limit,
the following occurs:
of the default registers after the ADT7475 is addressed via
any valid SMBus transaction.
If V CC goes high (the system processor power rail is
powered up), a fail-safe timer begins to count down. If the
ADT7475 is not addressed by any valid SMBus transactions
before the fail-safe timeout (4.6 seconds) lapses, the
ADT7475 drives the fans to full speed. If the ADT7475 is
addressed by a valid SMBus transaction after this point, the
fans stop, and the ADT7475 assumes its default settings and
begins normal operation.
If V CCP goes high (the system processor power rail is
powered up), then a fail-safe timer begins to count down. If
the ADT7475 is addressed by a valid SMBus transaction
before the fail-safe timeout (4.6 seconds) lapses, then the
ADT7475 operates normally, assuming the functionality of
all the default registers. See the flow chart in Figure 41.
ADT7475 IS POWERED UP
1. Status Bit 1 (V CCP ) in Status Register 1 is set.
2. SMBALERT is generated, if enabled.
3. THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
Y
HAS THE ADT7475 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
N
Once the core voltage, V CCP , goes above the V CCP low
limit, everything is re-enabled and the system resumes
normal operation.
XNOR Tree Test Mode
IS V CCP ABOVE 0.75 V?
Y
START FAIL-SAFE TIMER
N
CHECK V CCP
The ADT7475 includes an XNOR tree test mode. This
mode is useful for in-circuit test equipment at board-level
testing. By applying stimulus to the pins included in the
XNOR tree, it is possible to detect opens or shorts on the
system board.
Figure 40 shows the signals that are exercised in the XNOR
tree test mode. The XNOR tree test is invoked by setting Bit 0
(XEN) of the XNOR tree test enable register (0x6F).
Y
HAS THE ADT7475 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
N
FAIL-SAFE TIMER
ELAPSES AFTER THE
FAIL-SAFE TIMEOUT
TACH1
TACH2
HAS THE ADT7475 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
N
RUNS THE FANS
TO FULL SPEED
TACH3
TACH4
Y
HAS THE ADT7475 BEEN
ACCESSED BY A VALID
SMBus TRANSACTION?
N
Y
PWM2
START UP THE ADT7475
NORMALLY
SWITCH OFF FANS
PWM3
PWM1/XTO
Figure 41. Power-on Flow Chart
Figure 40. XNOR Tree Test
Power-On Default
When the ADT7475 is powered up, it polls the V CCP
input.
If V CCP stays below 0.75 V (the system CPU power rail
is not powered up), the ADT7475 assumes the functionality
Programming the Automatic Fan Speed Control Loop
To more efficiently understand the automatic fan speed
control loop, it is strongly recommended to use the ADT7475
evaluation board and software while reading this section.
This section provides the system designer with an
understanding of the automatic fan control loop, and
provides step-by-step guidance on effectively evaluating
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