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参数资料
| 型号： | ADUC7021BCPZ62-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 87/104页 |
| 文件大小： | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 40-LFCSP |
| 标准包装： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 连通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外围设备： | PLA，PWM，PSM，温度传感器，WDT |
| 输入/输出数： | 13 |
| 程序存储器容量： | 64KB（32K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2K x 32 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b，D/A 2x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 包装： | 带卷 (TR) |
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Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 83 of 104
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 23 interrupt sources on the ADuC7019/20/21/22/
24/25/26/27/28/29 that are controlled by the interrupt
controller. Most interrupts are generated from the on-chip
peripherals, such as ADC and UART. Four additional interrupt
sources are generated from external interrupt request pins,
IRQ0, IRQ1, IRQ2, and IRQ3. The ARM7TDMI CPU core only
recognizes interrupts as one of two types: a normal interrupt
request IRQ or a fast interrupt request FIQ. All the interrupts
can be masked separately.
The control and configuration of the interrupt system are
managed through nine interrupt-related registers, four
dedicated to IRQ, and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ register (except for Bit 23) represent
the same interrupt source as described in Table 160.
Table 160. IRQ/FIQ MMRs Bit Description
Bit
Description
0
All interrupts OR’ed (FIQ only)
1
SWI
2
Timer0
3
Timer1
4
Wake-up timer (Timer2)
5
Watchdog timer (Timer3)
6
Flash control
7
ADC channel
8
PLL lock
9
I2C0 slave
10
I2C0 master
11
I2C1 master
12
SPI slave
13
SPI master
14
UART
15
External IRQ0
16
Comparator
17
PSM
18
External IRQ1
19
PLA IRQ0
20
PLA IRQ1
21
External IRQ2
22
External IRQ3
23
PWM trip (IRQ only)/PWM sync (FIQ only)
IRQ
The interrupt request (IRQ) is the exception signal to enter the
IRQ mode of the processor. It is used to service general-purpose
interrupt handling of internal and external events.
The four 32-bit registers dedicated to IRQ are IRQSTA,
IRQSIG, IRQEN, and IRQCLR.
Table 161. IRQSTA Register
Name
Address
Default Value
Access
IRQSTA
0xFFFF0000
0x00000000
R
IRQSTA (read-only register) provides the current-enabled IRQ
source status. When set to 1, that source should generate an
active IRQ request to the ARM7TDMI core. There is no priority
encoder or interrupt vector generation. This function is
implemented in software in a common interrupt handler
routine. All 32 bits are logically OR’ed to create the IRQ signal
to the ARM7TDMI core.
Table 162. IRQSIG Register
Name
Address
Default Value
Access
IRQSIG
0xFFFF0004
0x00XXX0001
R
1
X indicates an undefined value.
IRQSIG reflects the status of the different IRQ sources. If a periph-
eral generates an IRQ signal, the corresponding bit in the IRQSIG
is set; otherwise, it is cleared. The IRQSIG bits are cleared when
the interrupt in the particular peripheral is cleared. All IRQ
sources can be masked in the IRQEN MMR. IRQSIG is read only.
Table 163. IRQEN Register
Name
Address
Default Value
Access
IRQEN
0xFFFF0008
0x00000000
R/W
IRQEN provides the value of the current enable mask. When
each bit is set to 1, the source request is enabled to create an
IRQ exception. When each bit is set to 0, the source request is
disabled or masked, which does not create an IRQ exception.
Note that to clear an already enabled interrupt source, the user
must set the appropriate bit in the IRQCLR register. Clearing an
interrupt’s IRQEN bit does not disable the interrupt.
Table 164. IRQCLR Register
Name
Address
Default Value
Access
IRQCLR
0xFFFF000C
0x00000000
W
IRQCLR (write-only register) clears the IRQEN register in
order to mask an interrupt source. Each bit set to 1 clears the
corresponding bit in the IRQEN register without affecting the
remaining bits. The pair of registers, IRQEN and IRQCLR,
independently manipulates the enable mask without requiring
an atomic read-modify-write.
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| ADUC7021BCPZ62-RL7 | 功能描述:IC MCU 12BIT 1MSPS UART 40-LFCSP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 标准包装:38 系列:Encore!® XP® 核心处理器:eZ8 芯体尺寸:8-位 速度:5MHz 连通性:IrDA，UART/USART 外围设备:欠压检测/复位，LED，POR，PWM，WDT 输入/输出数:16 程序存储器容量:4KB（4K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:1K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 3.6 V 数据转换器:- 振荡器型:内部 工作温度:-40°C ~ 105°C 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 包装:管件 其它名称:269-4116Z8F0413SH005EG-ND |
| ADUC7022 | 制造商:AD 制造商全称:Analog Devices 功能描述:Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| ADUC7022ACP32 | 制造商:Analog Devices 功能描述:FLASH ARM7+10-CH,12-B ADC IC - Trays |
| ADUC7022ACPZ32 | 制造商:Analog Devices 功能描述:MCU 32BIT RISC 32KB FLASH 3.3V 40LFCSP EP - Trays |
| ADUC7022BCP32 | 制造商:Analog Devices 功能描述:FLASH ARM7+10-CH,12-B ADC IC - Trays |
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