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| 型号： | ADV3227ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SW 16X16 100LFCSP |
| 标准包装： | 1 |
| 功能： | 交叉点开关 |
| 电路： | 1 x 16:16 |
| 电压电源： | 双电源 |
| 电压 - 电源，单路/双路(±)： | ±5V |
| 电流 - 电源： | 125mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 100ピンLFCSP-VQ（12x12） |
| 包装： | 管件 |
ADV3226/ADV3227
Rev. 0 | Page 21 of 24
THEORY OF OPERATION
The ADV3226 (G = 1) and ADV3227 (G = 2) are crosspoint
arrays with 16 outputs, each of which can be connected to any
one of 16 inputs. Organized by output row, 16 switchable input
transconductance stages are connected to each output buffer to
form 16-to-1 multiplexers. There are 16 of these multiplexers,
each with its inputs wired in parallel, for a total array of 256 trans-
conductance stages forming a multicast-capable crosspoint
switch. Each input is buffered and is not loaded by the outputs,
simplifying the construction of larger arrays using the ADV3226
or ADV3227 as a building block.
Decoding logic for each output selects one (or none) of the
transconductance stages to drive the output stage. The enabled
transconductance stage drives the output stage, and feedback
forms a closed-loop amplifier. A mask programmable feedback
network sets the closed-loop signal gain. For theADV3226, this
gain is 1, and for the ADV3226, this gain is 2.
The output stage of the ADV3226 or ADV3227 is designed for
low differential gain and phase error when driving composite
video signals. It also provides slew current for a fast pulse response
when driving component video signals. Unlike many multiplexer
designs, these requirements are balanced such that large signal
bandwidth is very similar to small signal bandwidth. The design
load is150 Ω, but provisions are made to drive loads as low as
100 Ω when on-chip power dissipation limits are not exceeded.
The outputs of the ADV3226/ADV3227 can be disabled to mini-
mize on-chip power dissipation. When disabled, there is no
feedback network loading the output. This high disabled output
impedance allows multiple ICs to be bussed together without
additional buffering. Care must be taken to reduce output capa-
citance, which results in more overshoot and frequency domain
peaking.
A series of internal amplifiers drives internal nodes such that a
wideband high impedance is presented at the disabled output,
even while the output bus is under large signal swings. To keep
these internal amplifiers in their linear range of operation when
the outputs are disabled and driven externally, do not allow the
voltage applied to them to exceed the valid output swing range
for the ADV3226/ADV3227. If the disabled outputs are left
floating, they may exhibit high enable glitches. If necessary,
the disabled output can be kept from drifting out of range by
applying an output load resistor to ground.
The connection of the ADV3226/ADV3227 is controlled by a
flexible TTL-compatible logic interface. Either parallel or serial
loading into a first rank of latches preprograms each output. A
global update signal moves the programming data into the second
rank of latches, simultaneously updating all outputs. In serial
mode, a serial out pin allows devices to be daisy-chained together
for single pin programming of multiple ICs. A power-on reset
pin is available to avoid bus conflicts by disabling all outputs.
This power-on reset clears the second rank of latches but does
not clear the first rank of latches. In serial mode, preprogramming
individual inputs is not possible and the entire shift register needs
to be flushed.
To easily interface to ground referenced video signals, the
ADV3226/ADV3227 operate on split ±5 V supplies. The logic
inputs and output run on a single +5 V supply, but the logic
inputs switch at approximately 1.6 V for compatibility with a
variety of logic families. The serial output buffer is a rail-to-rail
output stage with 5 mA of drive capability.
APPLICATIONS INFORMATION
The ADV3226/ADV3227 have two options for changing the
programming of the crosspoint matrix. In the first option, a
serial word of 80 bits can be provided, which updates the entire
matrix each time the 80-bit word is shifted into the part. The
second option allows for changing the programming of a single
output via a parallel interface. The serial option requires fewer
signals but more time (clock cycles) for changing the program-
ming, whereas the parallel programming technique requires
more signals but can change a single output at a time and requires
fewer clock cycles to complete the programming.
Serial Programming
The serial programming mode uses the CE, CLK, DATAIN,
UPDATE, and SER/PAR pins. The first step is to assert a low
on SER/PAR to enable the serial programming mode. CE for
the chip must be low to allow data to be clocked into the device.
The CE signal can be used to address an individual device when
devices are connected in parallel.
The UPDATE signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when UPDATE is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix, which causes
the matrix to try to update to every intermediate state as defined by
the shifting data.
The data at DATAIN is clocked in at every falling edge of CLK.
A total of 80 bits must be shifted in to complete the programming.
For each of the 16 outputs, there are four bits (D0 to D3) that deter-
mine the source of its input. The MSB is shifted in first. A fifth bit
(D4) precedes the four input select bits and determines the enabled
state of the output. If D4 is low (output disabled), the four asso-
ciated bits (D0 to D3) do not matter because no input switches
to that output.
The most significant output address data is shifted in first, and
the remaining addresses follow in sequence until the least signifi-
cant output address data is shifted in. At this point, UPDATE
can be taken low, which programs the device according to the
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADV3227-EVALZ | 制造商:AD 制造商全称:Analog Devices 功能描述:750 MHz, 16 × 16 Analog Crosspoint Switch |
| ADV3228ACPZ | 功能描述:IC CROSSPOINT SW 16X8 72LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 模拟开关，多路复用器，多路分解器 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 功能:开关 电路:单刀单掷 导通状态电阻:48 欧姆 电压电源:单电源 电压 - 电源，单路/双路(±):2.7 V ~ 5.5 V 电流 - 电源:5µA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:托盘 |
| ADV3229ACPZ | 功能描述:IC CROSSPOINT SW 16X8 72LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 模拟开关，多路复用器，多路分解器 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 功能:开关 电路:单刀单掷 导通状态电阻:48 欧姆 电压电源:单电源 电压 - 电源，单路/双路(±):2.7 V ~ 5.5 V 电流 - 电源:5µA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:托盘 |
| ADV32343001 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV32368102 | 制造商:LG Corporation 功能描述:Frame Assembly |
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